OpenCores
URL https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk

Subversion Repositories open8_urisc

[/] [open8_urisc/] [trunk/] - Rev 309

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
289 Added back the delay for the cursor home command, since it is slow on most Hitachi compatible LCD panels. jshamlet 1271d 21h /open8_urisc/trunk/
288 Removed hard-wired R/Wn output and replaced it with a note that the R/Wn line must be tied low either in firmware or on the board. jshamlet 1272d 17h /open8_urisc/trunk/
287 Fixed mangled comments and revisioning dates. jshamlet 1273d 16h /open8_urisc/trunk/
286 Added initial cut of a "universal" character LCD driver. Allows for adjustment of address setup, enable high, and cycle times. Also has built-in timers for handling timing on certain commands. jshamlet 1273d 17h /open8_urisc/trunk/
285 Added checksum byte to vector tx/rx to avoid issues with serial line noise glitching the receiver. Also modified the transmitted to take any generic argument, rather than canned arguments. jshamlet 1280d 20h /open8_urisc/trunk/
284 Corrected the vhdl unit name and description for o8_7seg.vhd jshamlet 1394d 07h /open8_urisc/trunk/
283 Altered SDLC bitclock check on TX to NOT block when tested by software, but to instead ignore packet write requests if BClk_Okay is low. This allows software to continue checking BClk_Okay in a polling loop. jshamlet 1397d 18h /open8_urisc/trunk/
282 Modified the SDLC core transmit states to have consistent naming. jshamlet 1397d 19h /open8_urisc/trunk/
281 Added pre-initialization to the dual-port RAM signals. jshamlet 1397d 21h /open8_urisc/trunk/
280 Got rid of silly aliases that connected the dual-port memory and the arbitration logic. jshamlet 1397d 22h /open8_urisc/trunk/

< Prev 1 2

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.