| Rev |
Log message |
Author |
Age |
Path |
| 259 |
Fixed issue where Write_Fault wasn't defaulting to '0' when Write_Protect was set to FALSE,
Added a pulse interval measurement entity,
Fixed comments. |
jshamlet |
1681d 19h |
/open8_urisc/trunk/VHDL/ |
| 258 |
Fixed write bug in o8_ltc2355_2p.vhd, added a newer Open8_cfg.vhd, and the sys_tick.vhd utility entity. |
jshamlet |
1682d 16h |
/open8_urisc/trunk/VHDL/ |
| 257 |
Fixed misnamed signal in o8_7seg.vhd and added a replacement switch interface that handles both static and pushbutton switches. |
jshamlet |
1682d 17h |
/open8_urisc/trunk/VHDL/ |
| 256 |
Removed unused generic from the status_led.vhd and cleaned up comments on the CPU |
jshamlet |
1682d 18h |
/open8_urisc/trunk/VHDL/ |
| 255 |
Modified code to make ModelSim happy (It didn't like the generate blocks for some reason). Also added a block describing the new generic. |
jshamlet |
1682d 23h |
/open8_urisc/trunk/VHDL/ |
| 254 |
Simplified the ISR address logic so that the upper 12 bits are constant (set by generic) and only the lower 4 bits are registered/computed. |
jshamlet |
1683d 13h |
/open8_urisc/trunk/VHDL/ |
| 253 |
Fixed spelling error in comment |
jshamlet |
1683d 14h |
/open8_urisc/trunk/VHDL/ |
| 252 |
(This time the CPU model was included...)
Added the ability to use unsigned offsets to the LDO/STO instructions. The original behavior of signed offsets is preserved if the Unsigned_Index_Offsets is left unset or set to FALSE. While inserting this code, pipeline registers were also inserted into the address generation logic for indexed instructions. This simplifies the final multiplexor and improves FMax at the slight expense of LDO/SDO now taking one additional clock cycle to execute. |
jshamlet |
1683d 14h |
/open8_urisc/trunk/VHDL/ |
| 251 |
Added RAM write fault detection, which can be used to indicate a memory write violation by the CPU. This allows a clean shutdown in the event of a memory problem/program crash.
Fixed a bug in the status_led.vhd entity that kept the flashing light function from working. The new code uses a maximal length 24-bit LFSR to create long delays. This is more efficient than a binary counter, but results in non-exact frequencies as a function of SYSTEM_FREQUENCY / (2^24-1).
Added the ability to use unsigned offsets to the LDO/STO instructions. The original behavior of signed offsets is preserved if the Unsigned_Index_Offsets is left unset or set to FALSE. While inserting this code, pipeline registers were also inserted into the address generation logic for indexed instructions. This simplifies the final multiplexor and improves FMax at the slight expense of LDO/SDO now taking one additional clock cycle to execute. |
jshamlet |
1683d 14h |
/open8_urisc/trunk/VHDL/ |
| 250 |
Removed monitor RAM from SDLC model, as it is now proven to work. |
jshamlet |
1687d 22h |
/open8_urisc/trunk/VHDL/ |
| 249 |
Added a 32-bit wide register and split the status_led core from o8_status_led.vhd, allowing it to be used as a subcomponent elsewhere. |
jshamlet |
1699d 14h |
/open8_urisc/trunk/VHDL/ |
| 248 |
Removed Default_Int_Flag generic from CPU, as it is duplicated by Supervisor_Mode. |
jshamlet |
1699d 22h |
/open8_urisc/trunk/VHDL/ |
| 247 |
Fixed problem where parallel interface was always forcing the data registers due to bad alias. |
jshamlet |
1700d 15h |
/open8_urisc/trunk/VHDL/ |
| 246 |
The system timer module now allows for an optional millisecond resolution (settable through a generic). This prescalar enable permits the timer to operate from 1 to 256 mS, which is useful for a variety of tasks, such as serial timeouts and watchdog timers. The enable is not software settable, as this would complicate the register interface and isn't generally useful in an HDL based SOC design.
The vector interface now has a parallel interface that runs beside the serial interface, and is useful for connecting to DIO cards or other parallel interfaces. |
jshamlet |
1700d 20h |
/open8_urisc/trunk/VHDL/ |
| 245 |
Modified the CPU's Supervisor_Mode to also protect SMSK and RSP instructions,
Added an external interrupt manager, o8_int_mgr.vhd. |
jshamlet |
1702d 19h |
/open8_urisc/trunk/VHDL/ |
| 244 |
Added two new generics to the CPU model. The first is a supervisory mode that disables the STP PSR_I instruction. This prevents errant code execution from setting the I bit, and disabling any subsequent memory protection logic. The second allows the default state of the I bit to be set at startup. If set true, initialization code will run with the I bit set, allowing it to bypass memory protection.
Also modified the RAM models to include write mask logic, where the mask register is write-protected by the I bit in the CPU. When enabled, the models will prevent code from writing to memory regions which do not have their mask bits set. The upshot is that code can effectively "write protect" the RAM - which is useful for multitasking applications.
Also, most modules have been updated with write qualification inputs, allowing a similar scheme to be used for I/O, though not as elegantly. I use a register module, whose own write qual line is attached to the external copy of the I bit as an I/O write protect register.
Lastly, added a new externally triggered timer, which can generate pulses with programmable delays and widths, and which can interrupt on either the input trigger, the output rising edge, or output falling edge. The time base can be either the internal microsecond tick signal, or an external clock. |
jshamlet |
1703d 15h |
/open8_urisc/trunk/VHDL/ |
| 243 |
Optimized code to prefer RAM vs register. |
jshamlet |
1710d 19h |
/open8_urisc/trunk/VHDL/ |
| 242 |
Added write protect logic to the RAM cores and system timer as part of scheme to keep tasks from messing up the scheduler or other task's memory. The RAM is now divided into regions with a separate write mask register. The write mask register itself is only writeable with the I bit is set (during an interrupt or by setting it using STP PSR_I). The 1K memory is divided into 16, 64 byte regions while the 4K memory is divided into 32, 128 byte regions. The system timer simply checks for the I bit being set when the write protect generic is set.
Note that setting the write_protect generic false, or leaving it unset, will keep the previous behavior. |
jshamlet |
1710d 19h |
/open8_urisc/trunk/VHDL/ |
| 241 |
Added an Open8 compatible 7-segment display/decoder and uploaded local/private documentation. |
jshamlet |
1715d 14h |
/open8_urisc/trunk/VHDL/ |
| 240 |
Simplified the vector tx/rx system to a single line. An idle detector replaces the attn_req signal. |
jshamlet |
1717d 18h |
/open8_urisc/trunk/VHDL/ |
| 231 |
Updated sample projects and added elapsed time capture (chronometer) module |
jshamlet |
1732d 22h |
/open8_urisc/trunk/VHDL/ |
| 229 |
Created a new version of the system timer with 24-bit, 1-uS resolution. The new timer has a much different register interface, so it is now o8_sys_timer_ii. |
jshamlet |
1736d 20h |
/open8_urisc/trunk/VHDL/ |
| 228 |
Added an initialization constant for the OPEN8_BUS_TYPE record. |
jshamlet |
1737d 10h |
/open8_urisc/trunk/VHDL/ |
| 227 |
Added a demonstration Open8_cfg.vhd file, which is used to configure the system constants. It also provides a function that makes it easy to merge read buses. |
jshamlet |
1737d 17h |
/open8_urisc/trunk/VHDL/ |
| 226 |
Forgot the updated package file... |
jshamlet |
1737d 20h |
/open8_urisc/trunk/VHDL/ |
| 225 |
Added Halt_Ack to go with Halt_Req. |
jshamlet |
1737d 20h |
/open8_urisc/trunk/VHDL/ |
| 224 |
Finished new Open8 bus record, which now includes the clock, reset and a microsecond tick. The CPU now accepts a clock and pll_locked signal, which it uses to generate the system reset in the bus record. It also contains a simple microsecond counter to feed the usec_tick in the record. This logic was removed from the real time clock and system timer entities, which now use the global version. Bus connections should be dramatically simplified, as only the read logic and interrupts are still run as separate signals. |
jshamlet |
1737d 22h |
/open8_urisc/trunk/VHDL/ |
| 223 |
Added an OPEN8_BUS_TYPE record to simplify connection to Open8 modules. The CPU now passes and Open8_Bus out, which supplies the bus address, write enable, write data, and read enable. Read data and interrupts are still handled as separate signals, since they are muxed/connected at the next level up. |
jshamlet |
1738d 15h |
/open8_urisc/trunk/VHDL/ |
| 222 |
Created a modified version of the epoch timer with a 32-bit, 1-uS resolution timer/comparator. |
jshamlet |
1738d 21h |
/open8_urisc/trunk/VHDL/ |
| 221 |
o8_vdsm8.vhd now has a default value assigned at compile time, o8_register.vhd was cleaned up some more. |
jshamlet |
1739d 15h |
/open8_urisc/trunk/VHDL/ |
