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[/] [open8_urisc/] [trunk/] [VHDL/] - Rev 268

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268 Added a 16-input external interrupt manager and dedicated SPI tx-only transmitter (for use with DACs, etc.). Also updated the soft-DACs with cleaned up HDL. jshamlet 1504d 09h /open8_urisc/trunk/VHDL/
267 Corrected the file description to indicate this is an example package. jshamlet 1504d 09h /open8_urisc/trunk/VHDL/
266 Accidentally uploaded incorrect example file for Open8_cfg.vhd jshamlet 1504d 09h /open8_urisc/trunk/VHDL/
265 Fixed a bug where "reg" wasn't being initialized with Poly_Init at reset. jshamlet 1596d 18h /open8_urisc/trunk/VHDL/
264 Updated comments jshamlet 1606d 15h /open8_urisc/trunk/VHDL/
263 Fixed a very old bug in the CPU core where autoincrements weren't affecting the upper register in the pair, causing it to loop around the lower 256 bytes. This only affected LDX/LDO, as the proper ALU signals were being generated in STO/STX and UPP. Wow, that bug has been in there for AGES.

Also separated the SDLC TX and RX interrupts so that they could be handled separately.
jshamlet 1606d 15h /open8_urisc/trunk/VHDL/
262 Added comments to LCD controllers - specifically that reading either register 0 or 1 will return the ready status. This code was already present, but not mentioned in the register map. jshamlet 1615d 19h /open8_urisc/trunk/VHDL/
261 Increased delay timer to 7 bits for button press detection. jshamlet 1622d 19h /open8_urisc/trunk/VHDL/
260 Added missing comments for Sequential_Interrupts generic, as well as comments explaining portions of the CPU operations. jshamlet 1635d 18h /open8_urisc/trunk/VHDL/
259 Fixed issue where Write_Fault wasn't defaulting to '0' when Write_Protect was set to FALSE,
Added a pulse interval measurement entity,
Fixed comments.
jshamlet 1635d 19h /open8_urisc/trunk/VHDL/
258 Fixed write bug in o8_ltc2355_2p.vhd, added a newer Open8_cfg.vhd, and the sys_tick.vhd utility entity. jshamlet 1636d 17h /open8_urisc/trunk/VHDL/
257 Fixed misnamed signal in o8_7seg.vhd and added a replacement switch interface that handles both static and pushbutton switches. jshamlet 1636d 18h /open8_urisc/trunk/VHDL/
256 Removed unused generic from the status_led.vhd and cleaned up comments on the CPU jshamlet 1636d 19h /open8_urisc/trunk/VHDL/
255 Modified code to make ModelSim happy (It didn't like the generate blocks for some reason). Also added a block describing the new generic. jshamlet 1636d 23h /open8_urisc/trunk/VHDL/
254 Simplified the ISR address logic so that the upper 12 bits are constant (set by generic) and only the lower 4 bits are registered/computed. jshamlet 1637d 14h /open8_urisc/trunk/VHDL/
253 Fixed spelling error in comment jshamlet 1637d 14h /open8_urisc/trunk/VHDL/
252 (This time the CPU model was included...)
Added the ability to use unsigned offsets to the LDO/STO instructions. The original behavior of signed offsets is preserved if the Unsigned_Index_Offsets is left unset or set to FALSE. While inserting this code, pipeline registers were also inserted into the address generation logic for indexed instructions. This simplifies the final multiplexor and improves FMax at the slight expense of LDO/SDO now taking one additional clock cycle to execute.
jshamlet 1637d 15h /open8_urisc/trunk/VHDL/
251 Added RAM write fault detection, which can be used to indicate a memory write violation by the CPU. This allows a clean shutdown in the event of a memory problem/program crash.

Fixed a bug in the status_led.vhd entity that kept the flashing light function from working. The new code uses a maximal length 24-bit LFSR to create long delays. This is more efficient than a binary counter, but results in non-exact frequencies as a function of SYSTEM_FREQUENCY / (2^24-1).

Added the ability to use unsigned offsets to the LDO/STO instructions. The original behavior of signed offsets is preserved if the Unsigned_Index_Offsets is left unset or set to FALSE. While inserting this code, pipeline registers were also inserted into the address generation logic for indexed instructions. This simplifies the final multiplexor and improves FMax at the slight expense of LDO/SDO now taking one additional clock cycle to execute.
jshamlet 1637d 15h /open8_urisc/trunk/VHDL/
250 Removed monitor RAM from SDLC model, as it is now proven to work. jshamlet 1641d 23h /open8_urisc/trunk/VHDL/
249 Added a 32-bit wide register and split the status_led core from o8_status_led.vhd, allowing it to be used as a subcomponent elsewhere. jshamlet 1653d 14h /open8_urisc/trunk/VHDL/

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