OpenCores
URL https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk

Subversion Repositories open8_urisc

[/] [open8_urisc/] [trunk/] [VHDL/] - Rev 273

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
273 Updated comments with corrections jshamlet 1495d 17h /open8_urisc/trunk/VHDL/
271 Removed deleted generic define. jshamlet 1505d 16h /open8_urisc/trunk/VHDL/
270 Moved CPU internal constants to o8_cpu.vhd and replace the generic that set the RSP direction flag with a constant instead. This removes the need to expose internal architectural flags externally.

Also added a hard-coded version register that takes a major and minor value as bytes using generics. This is a read-only register to the CPU.
jshamlet 1505d 16h /open8_urisc/trunk/VHDL/
269 Modified the write data path to use separate enumerated states rather than reuse the .reg field to improve performance. jshamlet 1508d 06h /open8_urisc/trunk/VHDL/
268 Added a 16-input external interrupt manager and dedicated SPI tx-only transmitter (for use with DACs, etc.). Also updated the soft-DACs with cleaned up HDL. jshamlet 1508d 07h /open8_urisc/trunk/VHDL/
267 Corrected the file description to indicate this is an example package. jshamlet 1508d 07h /open8_urisc/trunk/VHDL/
266 Accidentally uploaded incorrect example file for Open8_cfg.vhd jshamlet 1508d 07h /open8_urisc/trunk/VHDL/
265 Fixed a bug where "reg" wasn't being initialized with Poly_Init at reset. jshamlet 1600d 15h /open8_urisc/trunk/VHDL/
264 Updated comments jshamlet 1610d 13h /open8_urisc/trunk/VHDL/
263 Fixed a very old bug in the CPU core where autoincrements weren't affecting the upper register in the pair, causing it to loop around the lower 256 bytes. This only affected LDX/LDO, as the proper ALU signals were being generated in STO/STX and UPP. Wow, that bug has been in there for AGES.

Also separated the SDLC TX and RX interrupts so that they could be handled separately.
jshamlet 1610d 13h /open8_urisc/trunk/VHDL/
262 Added comments to LCD controllers - specifically that reading either register 0 or 1 will return the ready status. This code was already present, but not mentioned in the register map. jshamlet 1619d 16h /open8_urisc/trunk/VHDL/
261 Increased delay timer to 7 bits for button press detection. jshamlet 1626d 16h /open8_urisc/trunk/VHDL/
260 Added missing comments for Sequential_Interrupts generic, as well as comments explaining portions of the CPU operations. jshamlet 1639d 15h /open8_urisc/trunk/VHDL/
259 Fixed issue where Write_Fault wasn't defaulting to '0' when Write_Protect was set to FALSE,
Added a pulse interval measurement entity,
Fixed comments.
jshamlet 1639d 17h /open8_urisc/trunk/VHDL/
258 Fixed write bug in o8_ltc2355_2p.vhd, added a newer Open8_cfg.vhd, and the sys_tick.vhd utility entity. jshamlet 1640d 15h /open8_urisc/trunk/VHDL/
257 Fixed misnamed signal in o8_7seg.vhd and added a replacement switch interface that handles both static and pushbutton switches. jshamlet 1640d 15h /open8_urisc/trunk/VHDL/
256 Removed unused generic from the status_led.vhd and cleaned up comments on the CPU jshamlet 1640d 16h /open8_urisc/trunk/VHDL/
255 Modified code to make ModelSim happy (It didn't like the generate blocks for some reason). Also added a block describing the new generic. jshamlet 1640d 21h /open8_urisc/trunk/VHDL/
254 Simplified the ISR address logic so that the upper 12 bits are constant (set by generic) and only the lower 4 bits are registered/computed. jshamlet 1641d 12h /open8_urisc/trunk/VHDL/
253 Fixed spelling error in comment jshamlet 1641d 12h /open8_urisc/trunk/VHDL/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.