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[/] [open8_urisc/] [trunk/] [VHDL/] [async_ser_rx.vhd] - Rev 294

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294 Fixed an ancient bug in the parity logic that had the parity inverted. jshamlet 1184d 19h /open8_urisc/trunk/VHDL/async_ser_rx.vhd
220 More revision sections added jshamlet 1701d 14h /open8_urisc/trunk/VHDL/async_ser_rx.vhd
218 Revision sections added,
vdsm8.vhd added.
jshamlet 1701d 14h /open8_urisc/trunk/VHDL/async_ser_rx.vhd
215 More code cleanup jshamlet 1701d 17h /open8_urisc/trunk/VHDL/async_ser_rx.vhd
209 Fixed an issue in the PIT timer that caused an immediate interrupt on interval write,
Fixed an issue in the epoch timer that resulted in a spurious interrupt due to extra LSB's being set by default in the set point register,
While cleaning elsewhere, founding a spacing issue in the CPU HDL,
Added a 4k ROM and MW core.
jshamlet 1707d 10h /open8_urisc/trunk/VHDL/async_ser_rx.vhd
208 Removed unnecessary package references jshamlet 1707d 19h /open8_urisc/trunk/VHDL/async_ser_rx.vhd
207 Added a simple 8-bit, fixed asynchronous serial interface with compile time settable bit-rate, parity enable, and parity mode generics. jshamlet 1708d 13h /open8_urisc/trunk/VHDL/async_ser_rx.vhd

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