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[/] [open8_urisc/] [trunk/] [VHDL/] [o8_cpu.vhd] - Rev 264

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264 Updated comments jshamlet 1614d 14h /open8_urisc/trunk/VHDL/o8_cpu.vhd
263 Fixed a very old bug in the CPU core where autoincrements weren't affecting the upper register in the pair, causing it to loop around the lower 256 bytes. This only affected LDX/LDO, as the proper ALU signals were being generated in STO/STX and UPP. Wow, that bug has been in there for AGES.

Also separated the SDLC TX and RX interrupts so that they could be handled separately.
jshamlet 1614d 14h /open8_urisc/trunk/VHDL/o8_cpu.vhd
260 Added missing comments for Sequential_Interrupts generic, as well as comments explaining portions of the CPU operations. jshamlet 1643d 17h /open8_urisc/trunk/VHDL/o8_cpu.vhd
256 Removed unused generic from the status_led.vhd and cleaned up comments on the CPU jshamlet 1644d 18h /open8_urisc/trunk/VHDL/o8_cpu.vhd
255 Modified code to make ModelSim happy (It didn't like the generate blocks for some reason). Also added a block describing the new generic. jshamlet 1644d 22h /open8_urisc/trunk/VHDL/o8_cpu.vhd
254 Simplified the ISR address logic so that the upper 12 bits are constant (set by generic) and only the lower 4 bits are registered/computed. jshamlet 1645d 13h /open8_urisc/trunk/VHDL/o8_cpu.vhd
253 Fixed spelling error in comment jshamlet 1645d 13h /open8_urisc/trunk/VHDL/o8_cpu.vhd
252 (This time the CPU model was included...)
Added the ability to use unsigned offsets to the LDO/STO instructions. The original behavior of signed offsets is preserved if the Unsigned_Index_Offsets is left unset or set to FALSE. While inserting this code, pipeline registers were also inserted into the address generation logic for indexed instructions. This simplifies the final multiplexor and improves FMax at the slight expense of LDO/SDO now taking one additional clock cycle to execute.
jshamlet 1645d 14h /open8_urisc/trunk/VHDL/o8_cpu.vhd
248 Removed Default_Int_Flag generic from CPU, as it is duplicated by Supervisor_Mode. jshamlet 1661d 21h /open8_urisc/trunk/VHDL/o8_cpu.vhd
245 Modified the CPU's Supervisor_Mode to also protect SMSK and RSP instructions,
Added an external interrupt manager, o8_int_mgr.vhd.
jshamlet 1664d 19h /open8_urisc/trunk/VHDL/o8_cpu.vhd
244 Added two new generics to the CPU model. The first is a supervisory mode that disables the STP PSR_I instruction. This prevents errant code execution from setting the I bit, and disabling any subsequent memory protection logic. The second allows the default state of the I bit to be set at startup. If set true, initialization code will run with the I bit set, allowing it to bypass memory protection.

Also modified the RAM models to include write mask logic, where the mask register is write-protected by the I bit in the CPU. When enabled, the models will prevent code from writing to memory regions which do not have their mask bits set. The upshot is that code can effectively "write protect" the RAM - which is useful for multitasking applications.

Also, most modules have been updated with write qualification inputs, allowing a similar scheme to be used for I/O, though not as elegantly. I use a register module, whose own write qual line is attached to the external copy of the I bit as an I/O write protect register.

Lastly, added a new externally triggered timer, which can generate pulses with programmable delays and widths, and which can interrupt on either the input trigger, the output rising edge, or output falling edge. The time base can be either the internal microsecond tick signal, or an external clock.
jshamlet 1665d 15h /open8_urisc/trunk/VHDL/o8_cpu.vhd
227 Added a demonstration Open8_cfg.vhd file, which is used to configure the system constants. It also provides a function that makes it easy to merge read buses. jshamlet 1699d 16h /open8_urisc/trunk/VHDL/o8_cpu.vhd
225 Added Halt_Ack to go with Halt_Req. jshamlet 1699d 20h /open8_urisc/trunk/VHDL/o8_cpu.vhd
224 Finished new Open8 bus record, which now includes the clock, reset and a microsecond tick. The CPU now accepts a clock and pll_locked signal, which it uses to generate the system reset in the bus record. It also contains a simple microsecond counter to feed the usec_tick in the record. This logic was removed from the real time clock and system timer entities, which now use the global version. Bus connections should be dramatically simplified, as only the read logic and interrupts are still run as separate signals. jshamlet 1699d 22h /open8_urisc/trunk/VHDL/o8_cpu.vhd
223 Added an OPEN8_BUS_TYPE record to simplify connection to Open8 modules. The CPU now passes and Open8_Bus out, which supplies the bus address, write enable, write data, and read enable. Read data and interrupts are still handled as separate signals, since they are muxed/connected at the next level up. jshamlet 1700d 15h /open8_urisc/trunk/VHDL/o8_cpu.vhd
210 Modified the timers to reset on new interval write. This avoids an issue in the original design where the timer had to reach zero before updating, potentially causing unwanted interrupts.
Also added a flag to the CPU to allow interrupts to be processed sequentially based on the state of the I bit. This one is set to false by default, as it is a significant change in interrupt behavior. Long, and reentrant, ISRs can clear the I bit prematurely to allow themselves to be interrupted.
Lastly, added the I bit to the exported flags for possible use in memory protection schemes.
jshamlet 1706d 23h /open8_urisc/trunk/VHDL/o8_cpu.vhd
209 Fixed an issue in the PIT timer that caused an immediate interrupt on interval write,
Fixed an issue in the epoch timer that resulted in a spurious interrupt due to extra LSB's being set by default in the set point register,
While cleaning elsewhere, founding a spacing issue in the CPU HDL,
Added a 4k ROM and MW core.
jshamlet 1707d 12h /open8_urisc/trunk/VHDL/o8_cpu.vhd
194 Cleaned up licensing sections jshamlet 1715d 18h /open8_urisc/trunk/VHDL/o8_cpu.vhd
191 Cleaned up comments, added back the OPEN8_NULLBUS constant, and added some new modules for ADCs and LCD displays.
Also made the button input module more configurable by moving the debounce code to a separate entity and using generics to instantiate it.
jshamlet 1715d 18h /open8_urisc/trunk/VHDL/o8_cpu.vhd
190 Fixed a bug in CPU where RTI/RTS wasn't idling the instruction cache, causing intermittent failures where RTI would execute as RTS, corrupting the stack;
Fixed a bug in the real-time clock where the uSec tick generator would stop if the PIT timer value was left/set to 0x00.
jshamlet 1727d 16h /open8_urisc/trunk/VHDL/o8_cpu.vhd

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