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[/] [open8_urisc/] [trunk/] [VHDL/] [o8_cpu.vhd] - Rev 298

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209 Fixed an issue in the PIT timer that caused an immediate interrupt on interval write,
Fixed an issue in the epoch timer that resulted in a spurious interrupt due to extra LSB's being set by default in the set point register,
While cleaning elsewhere, founding a spacing issue in the CPU HDL,
Added a 4k ROM and MW core.
jshamlet 1699d 21h /open8_urisc/trunk/VHDL/o8_cpu.vhd
194 Cleaned up licensing sections jshamlet 1708d 03h /open8_urisc/trunk/VHDL/o8_cpu.vhd
191 Cleaned up comments, added back the OPEN8_NULLBUS constant, and added some new modules for ADCs and LCD displays.
Also made the button input module more configurable by moving the debounce code to a separate entity and using generics to instantiate it.
jshamlet 1708d 04h /open8_urisc/trunk/VHDL/o8_cpu.vhd
190 Fixed a bug in CPU where RTI/RTS wasn't idling the instruction cache, causing intermittent failures where RTI would execute as RTS, corrupting the stack;
Fixed a bug in the real-time clock where the uSec tick generator would stop if the PIT timer value was left/set to 0x00.
jshamlet 1720d 02h /open8_urisc/trunk/VHDL/o8_cpu.vhd
188 Added a generic to alter the behavior of RTI so that it can optionally skip restoring the general purpose flags GP4 to GP7, allowing ISR's to make persistent changes to them. Also exported these flags to the top level for use outside the CPU. jshamlet 1721d 05h /open8_urisc/trunk/VHDL/o8_cpu.vhd
187 Added the CPU_Halt input, only now as an input to the instruction decoder. The CPU_Halt line will assert the registered CPU_Halt_Req, which will cause the instruction decoder to abort the current instruction, reset the PC, then enter a hold state until the line is deasserted. Additionally, a very minor bug that could cause the SMSK instruction to effectively execute twice if interrupted was fixed. Lastly, cleaned up the comments even more. jshamlet 1723d 01h /open8_urisc/trunk/VHDL/o8_cpu.vhd
186 Merged the interrupt override logic into the case structure, simplifying how interrupts are processed. jshamlet 1726d 01h /open8_urisc/trunk/VHDL/o8_cpu.vhd
185 1) Fixed an apparently long-standing bug where the interrupt bit wasn't being cleared after an RTI
2) Modified the program counter logic to be simpler. It now always increments, and states control the increment using the offset field. A new set of constants was added to replace the old states.
3) Modified the ALU to always use Operand1 instead of ALU_Ctrl.Data (and removed the field in the record). A new ALU command, ALU_GMSK, was added, as it was the only instruction to set the .Data field to something other than Operand1 (Int_Mask)
4) Modified the package file so that flag names match what the assembler calls them. FL_Z is now PSR_Z, FL_GP1 is now PSR_GP4, etc.
5) Cleaned up the comments and code formatting
jshamlet 1726d 04h /open8_urisc/trunk/VHDL/o8_cpu.vhd
183 Renamed core to o8_cpu to match new naming scheme jshamlet 1728d 04h /open8_urisc/trunk/VHDL/o8_cpu.vhd
182 Simplified the address generation logic at the expense of making LDX take one additional clock cycle. This allowed the address logic to be split out of the main state machine and simplified (greatly). During this process, a bug in SDO was found and fixed that caused it to return through the wrong pipe fill state wnen auto increment was disabled. jshamlet 1728d 04h /open8_urisc/trunk/VHDL/Open8.vhd

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