OpenCores
URL https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk

Subversion Repositories open8_urisc

[/] [open8_urisc/] [trunk/] [VHDL/] [o8_cpu.vhd] - Rev 309

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
298 Fixed a long-standing bug in the SBC instruction where the 1 wasn't being added to complete the 2's complement of Rn. This was causing off-by-one errors in subtraction and negating carry only subtractions. jshamlet 816d 00h /open8_urisc/trunk/VHDL/o8_cpu.vhd
290 Added an additional generic "Rotation_Ignores_Carry" that removes the carry logic from the ROL/ROR instructions such that they now rotate 'normally',
Added an alias for PSR_GP4 named PSR_S, as it is now used to switch the function of the RSP instruction. The internal opcode hasn't changed, but it allows assembly code to use PSR_S or BRS/BNS when performing RSP related operations.
jshamlet 1250d 22h /open8_urisc/trunk/VHDL/o8_cpu.vhd
270 Moved CPU internal constants to o8_cpu.vhd and replace the generic that set the RSP direction flag with a constant instead. This removes the need to expose internal architectural flags externally.

Also added a hard-coded version register that takes a major and minor value as bytes using generics. This is a read-only register to the CPU.
jshamlet 1443d 06h /open8_urisc/trunk/VHDL/o8_cpu.vhd
269 Modified the write data path to use separate enumerated states rather than reuse the .reg field to improve performance. jshamlet 1445d 19h /open8_urisc/trunk/VHDL/o8_cpu.vhd
264 Updated comments jshamlet 1548d 02h /open8_urisc/trunk/VHDL/o8_cpu.vhd
263 Fixed a very old bug in the CPU core where autoincrements weren't affecting the upper register in the pair, causing it to loop around the lower 256 bytes. This only affected LDX/LDO, as the proper ALU signals were being generated in STO/STX and UPP. Wow, that bug has been in there for AGES.

Also separated the SDLC TX and RX interrupts so that they could be handled separately.
jshamlet 1548d 02h /open8_urisc/trunk/VHDL/o8_cpu.vhd
260 Added missing comments for Sequential_Interrupts generic, as well as comments explaining portions of the CPU operations. jshamlet 1577d 05h /open8_urisc/trunk/VHDL/o8_cpu.vhd
256 Removed unused generic from the status_led.vhd and cleaned up comments on the CPU jshamlet 1578d 06h /open8_urisc/trunk/VHDL/o8_cpu.vhd
255 Modified code to make ModelSim happy (It didn't like the generate blocks for some reason). Also added a block describing the new generic. jshamlet 1578d 10h /open8_urisc/trunk/VHDL/o8_cpu.vhd
254 Simplified the ISR address logic so that the upper 12 bits are constant (set by generic) and only the lower 4 bits are registered/computed. jshamlet 1579d 01h /open8_urisc/trunk/VHDL/o8_cpu.vhd
253 Fixed spelling error in comment jshamlet 1579d 01h /open8_urisc/trunk/VHDL/o8_cpu.vhd
252 (This time the CPU model was included...)
Added the ability to use unsigned offsets to the LDO/STO instructions. The original behavior of signed offsets is preserved if the Unsigned_Index_Offsets is left unset or set to FALSE. While inserting this code, pipeline registers were also inserted into the address generation logic for indexed instructions. This simplifies the final multiplexor and improves FMax at the slight expense of LDO/SDO now taking one additional clock cycle to execute.
jshamlet 1579d 01h /open8_urisc/trunk/VHDL/o8_cpu.vhd
248 Removed Default_Int_Flag generic from CPU, as it is duplicated by Supervisor_Mode. jshamlet 1595d 09h /open8_urisc/trunk/VHDL/o8_cpu.vhd
245 Modified the CPU's Supervisor_Mode to also protect SMSK and RSP instructions,
Added an external interrupt manager, o8_int_mgr.vhd.
jshamlet 1598d 07h /open8_urisc/trunk/VHDL/o8_cpu.vhd
244 Added two new generics to the CPU model. The first is a supervisory mode that disables the STP PSR_I instruction. This prevents errant code execution from setting the I bit, and disabling any subsequent memory protection logic. The second allows the default state of the I bit to be set at startup. If set true, initialization code will run with the I bit set, allowing it to bypass memory protection.

Also modified the RAM models to include write mask logic, where the mask register is write-protected by the I bit in the CPU. When enabled, the models will prevent code from writing to memory regions which do not have their mask bits set. The upshot is that code can effectively "write protect" the RAM - which is useful for multitasking applications.

Also, most modules have been updated with write qualification inputs, allowing a similar scheme to be used for I/O, though not as elegantly. I use a register module, whose own write qual line is attached to the external copy of the I bit as an I/O write protect register.

Lastly, added a new externally triggered timer, which can generate pulses with programmable delays and widths, and which can interrupt on either the input trigger, the output rising edge, or output falling edge. The time base can be either the internal microsecond tick signal, or an external clock.
jshamlet 1599d 03h /open8_urisc/trunk/VHDL/o8_cpu.vhd
227 Added a demonstration Open8_cfg.vhd file, which is used to configure the system constants. It also provides a function that makes it easy to merge read buses. jshamlet 1633d 04h /open8_urisc/trunk/VHDL/o8_cpu.vhd
225 Added Halt_Ack to go with Halt_Req. jshamlet 1633d 08h /open8_urisc/trunk/VHDL/o8_cpu.vhd
224 Finished new Open8 bus record, which now includes the clock, reset and a microsecond tick. The CPU now accepts a clock and pll_locked signal, which it uses to generate the system reset in the bus record. It also contains a simple microsecond counter to feed the usec_tick in the record. This logic was removed from the real time clock and system timer entities, which now use the global version. Bus connections should be dramatically simplified, as only the read logic and interrupts are still run as separate signals. jshamlet 1633d 10h /open8_urisc/trunk/VHDL/o8_cpu.vhd
223 Added an OPEN8_BUS_TYPE record to simplify connection to Open8 modules. The CPU now passes and Open8_Bus out, which supplies the bus address, write enable, write data, and read enable. Read data and interrupts are still handled as separate signals, since they are muxed/connected at the next level up. jshamlet 1634d 03h /open8_urisc/trunk/VHDL/o8_cpu.vhd
210 Modified the timers to reset on new interval write. This avoids an issue in the original design where the timer had to reach zero before updating, potentially causing unwanted interrupts.
Also added a flag to the CPU to allow interrupts to be processed sequentially based on the state of the I bit. This one is set to false by default, as it is a significant change in interrupt behavior. Long, and reentrant, ISRs can clear the I bit prematurely to allow themselves to be interrupted.
Lastly, added the I bit to the exported flags for possible use in memory protection schemes.
jshamlet 1640d 11h /open8_urisc/trunk/VHDL/o8_cpu.vhd

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.