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[/] [open8_urisc/] [trunk/] [VHDL/] [o8_sdlc_if.vhd] - Rev 244

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244 Added two new generics to the CPU model. The first is a supervisory mode that disables the STP PSR_I instruction. This prevents errant code execution from setting the I bit, and disabling any subsequent memory protection logic. The second allows the default state of the I bit to be set at startup. If set true, initialization code will run with the I bit set, allowing it to bypass memory protection.

Also modified the RAM models to include write mask logic, where the mask register is write-protected by the I bit in the CPU. When enabled, the models will prevent code from writing to memory regions which do not have their mask bits set. The upshot is that code can effectively "write protect" the RAM - which is useful for multitasking applications.

Also, most modules have been updated with write qualification inputs, allowing a similar scheme to be used for I/O, though not as elegantly. I use a register module, whose own write qual line is attached to the external copy of the I bit as an I/O write protect register.

Lastly, added a new externally triggered timer, which can generate pulses with programmable delays and widths, and which can interrupt on either the input trigger, the output rising edge, or output falling edge. The time base can be either the internal microsecond tick signal, or an external clock.
jshamlet 1662d 04h /open8_urisc/trunk/VHDL/o8_sdlc_if.vhd
224 Finished new Open8 bus record, which now includes the clock, reset and a microsecond tick. The CPU now accepts a clock and pll_locked signal, which it uses to generate the system reset in the bus record. It also contains a simple microsecond counter to feed the usec_tick in the record. This logic was removed from the real time clock and system timer entities, which now use the global version. Bus connections should be dramatically simplified, as only the read logic and interrupts are still run as separate signals. jshamlet 1696d 11h /open8_urisc/trunk/VHDL/o8_sdlc_if.vhd
223 Added an OPEN8_BUS_TYPE record to simplify connection to Open8 modules. The CPU now passes and Open8_Bus out, which supplies the bus address, write enable, write data, and read enable. Read data and interrupts are still handled as separate signals, since they are muxed/connected at the next level up. jshamlet 1697d 04h /open8_urisc/trunk/VHDL/o8_sdlc_if.vhd
206 Merged interrupt logic with other clocked process. jshamlet 1708d 22h /open8_urisc/trunk/VHDL/o8_sdlc_if.vhd
205 More code and comment cleanup for the new SDLC engine jshamlet 1708d 22h /open8_urisc/trunk/VHDL/o8_sdlc_if.vhd
204 Fixed more incorrect comments jshamlet 1708d 23h /open8_urisc/trunk/VHDL/o8_sdlc_if.vhd
202 Fixed receiver bug that caused false flag detection,
Split the large sdlc_serial_ctrl entity into sub-entities to make debugging easier.
jshamlet 1709d 06h /open8_urisc/trunk/VHDL/o8_sdlc_if.vhd
201 Fixed comments regarding RX Checksum location jshamlet 1711d 03h /open8_urisc/trunk/VHDL/o8_sdlc_if.vhd
200 Renamed dual-port buffer to match other entities. jshamlet 1711d 03h /open8_urisc/trunk/VHDL/o8_sdlc_if.vhd
199 Added monitor ram for debugging and fixed issue with dual-port read path. jshamlet 1711d 03h /open8_urisc/trunk/VHDL/o8_sdlc_if.vhd
198 Removed debugging memory jshamlet 1711d 11h /open8_urisc/trunk/VHDL/o8_sdlc_if.vhd
196 Modified the update logic to allow direct writes to offset 0xFE for refreshing the clock status. This way, any write to the clock status register will immediately be undone. (Writing 0x00 to offset 0xFF is once-more ignored) jshamlet 1711d 12h /open8_urisc/trunk/VHDL/o8_sdlc_if.vhd
192 Added SDLC packet engine jshamlet 1712d 08h /open8_urisc/trunk/VHDL/o8_sdlc_if.vhd

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