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[/] [openarty/] [trunk/] [rtl/] [eqspiflash.v] - Rev 44

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44 Fixed the flash so that it now runs in 1) high speed (41MHz), and 2) that it
doesn't struggle to do read bursts. This should greatly speed up access time.
dgisselq 2701d 19h /openarty/trunk/rtl/eqspiflash.v
20 Lots of bug fixes: After turning on XIP, and running in XIP mode, leaving XIP
mode turns it back off again, necessitating a new write to the VCon register.
Further, XIP mode starts in extended SPI mode, and only transfers in QSPI
mode for data. Finally, two new commands have been created: enabling the
SPI memory reset, and actually resetting the SPI memory. In general, these
are all better--as the EQSPI flash controller now works with these changes,
whereby it didn't really work without them before.
dgisselq 2783d 19h /openarty/trunk/rtl/eqspiflash.v
13 Here are the updates necessary to get the initial Quad SPI flash driver working.
This includes in particular the bus interconnect (in fastmaster.v), and the
final hookup to the external wires (in fasttop.v).
dgisselq 2785d 20h /openarty/trunk/rtl/eqspiflash.v
12 A work in progress. This checkin contains fixes for the flash (mostly),
together with some logic reductions facilitating full speed (200MHz) build.
dgisselq 2786d 23h /openarty/trunk/rtl/eqspiflash.v
3 Initial set of files. The flash appears to work, memory hasn't been started,
the MDIO controller works in simulation, etc. Everything below fasttop.v works
at 200MHz (not the CPU---yet).
dgisselq 2802d 03h /openarty/trunk/rtl/eqspiflash.v

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