| Rev |
Log message |
Author |
Age |
Path |
| 815 |
OR1200 debug unit: prevent deadlock when trap instruction stalls
As per mailing list post <20120925160925.5725e06f@latmask.vernier.se>,
the debug unit could deadlock with the instruction decoder if the trap
instruction is held back by a pipeline stall. This change prevents that.
The problem can be reproduced by placing a breakpoint at an unfavorable
position with instruction cache enabled. In our test, this occurred
with or1200-cbasic when placing a breakpoint at test_bss using gdb, but
this is dependent on such factors as cache parameters and compilation
result. |
yannv |
4603d 01h |
/ |
| 814 |
orpsoc/or1200: Set correct PC after reset when parameter boot_adr is used
Signed-off-by: Olof Kindgren <olof@opencores.org>
Acked-by: Julius Baxter <juliusbaxter@gmail.com> |
olof |
4617d 18h |
/ |
| 813 |
or1200: Set correct PC after reset when parameter boot_adr is used
Signed-off-by: Olof Kindgren <olof@opencores.org>
Acked-by: Julius Baxter <juliusbaxter@gmail.com> |
olof |
4617d 18h |
/ |
| 812 |
Fix for Bug 86 - Problem with or1k_interrupt_handler_add() |
stekern |
4682d 02h |
/ |
| 811 |
added exec command to redboot |
skrzyp |
4720d 23h |
/ |
| 810 |
Added SPI driver |
skrzyp |
4722d 23h |
/ |
| 809 |
OR1200: Regenerate documentation.
Forgot newline in version history table, so last entry was missing. |
julius |
4733d 11h |
/ |
| 808 |
OR1200: Add DSX bit support to SR.
Updated documentation, revision is now 13.
http://bugzilla.opencores.org/bugzilla4/show_bug.cgi?id=85 |
julius |
4733d 11h |
/ |
| 807 |
ORPSoC: Commit for bug 85 - add DSX support to OR1200.
http://bugzilla.opencores.org/bugzilla4/show_bug.cgi?id=85
Also added software tests, and added these tests to default regression test list |
julius |
4733d 12h |
/ |
| 806 |
OR1200: Fix for bug 90
http://bugzilla.opencores.org/bugzilla4/show_bug.cgi?id=90 |
julius |
4733d 12h |
/ |
| 805 |
ORPSoC: Fix for bug 90 - EPCR on range exception bug
http://bugzilla.opencores.org/bugzilla4/show_bug.cgi?id=90 |
julius |
4733d 12h |
/ |
| 804 |
OR1200: Fix for bug 91
http://bugzilla.opencores.org/bugzilla4/show_bug.cgi?id=91 |
julius |
4733d 12h |
/ |
| 803 |
ORPSoC: Fix for bug 91, l.sub not setting overflow flag correctly
http://bugzilla.opencores.org/bugzilla4/show_bug.cgi?id=91 |
julius |
4733d 12h |
/ |
| 802 |
OR1200: Fix for bug 88
http://bugzilla.opencores.org/bugzilla4/show_bug.cgi?id=88 |
julius |
4738d 17h |
/ |
| 801 |
ORPSoC: Fix bug 88
http://bugzilla.opencores.org/bugzilla4/show_bug.cgi?id=88 |
julius |
4738d 17h |
/ |
| 800 |
FreeRTOSV6.1.1
add or32_dma demo task for test dcache manuplation function
add simple driver of wb_dma |
filepang |
4751d 08h |
/ |
| 799 |
FreeRTOSV6.1.1
add cache related function from u-boot from OpenRISC
enable I/D cache if present |
filepang |
4752d 09h |
/ |
| 798 |
Added drivers for ethmac and sdcard_mass_storage_controller |
skrzyp |
4754d 18h |
/ |
| 797 |
testsuite: kill test processes that timeout |
pgavin |
4762d 23h |
/ |
| 796 |
Correct orpmon show_rx_buffs and show_mac_regs to use TX_BD_NUM properly. |
yannv |
4766d 02h |
/ |
| 795 |
Created or1200_rel3 branch from rev 794 |
olof |
4766d 17h |
/ |
| 794 |
ORPSoC, or1200: split out or1200_fpu_intfloat_conv_except module into own file
Fixes lint warnings. |
julius |
4772d 03h |
/ |
| 793 |
Corrected Julius Baxter's email address in MAINTAINERS |
jeremybennett |
4783d 02h |
/ |
| 792 |
Added a MAINTAINERS file.
012-04-07 Jeremy Bennett <jeremy.bennett@embecosm.com>
* MAINTAINERS: Added.
* configure: Regenerated.
* configure.ac: Updated version. |
jeremybennett |
4783d 02h |
/ |
| 791 |
Added options to configure RAM and ROM sizes. Fixed cache handling. |
skrzyp |
4785d 20h |
/ |
| 790 |
fixed issues with context switching, interrupts, optimizations and cleanups |
skrzyp |
4792d 21h |
/ |
| 789 |
ORPSoC: Patch from R Diez to make RTL sim report l.nops have equivalent formatting to those from or1ksim
Signed-off-by: R Diez <rdiezmail-openrisc@yahoo.de>
Acked-by: Julius Baxter <juliusbaxter@gmail.com> |
julius |
4796d 16h |
/ |
| 788 |
or1200: Patch from R Diez to remove l.cust5 signal from a sensitivty list when it's not defined.
Signed-off-by: R Diez <rdiezmail-openrisc@yahoo.de>
Acked-by: Julius Baxter <juliusbaxter@gmail.com> |
julius |
4796d 17h |
/ |
| 787 |
Patch from R Diez to zero R0 on startup. ChangeLog from testsuite/test-code-or1k:
2012-03-23 Jeremy Bennett <jeremy.bennett@embecosm.com>
Patch from R Diez <rdiezmail-openrisc@yahoo.de>
* cache/cache-asm.S, cfg/cfg.S, except-test/except-test-s.S,
* except/except.S, ext/ext.S, flag/flag.S, fp/fp.S,
* inst-set-test/inst-set-test.S, int-test/int-test.S,
* mc-common/except-mc.S, uos/except-or32.S: Clear R0 on
start-up. There is no guarantee that R0 is hardwired to zero, and
indeed it is not when simulating the or1200 Verilog core.
* configure: Regenerated.
* configure.ac: Updated version. |
jeremybennett |
4798d 01h |
/ |
| 786 |
new ecos tree (tracking mainline) |
skrzyp |
4798d 01h |
/ |
