URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] - Rev 135

Rev	Log message	Author	Age	Path
115	Added support for l.fl1 and tests for l.ff1 and l.fl1	jeremybennett	5846d 18h	/openrisc/
114	l.addic added. Tests of l.add, l.addc, l.addi and l.addic completed. All set overflow correctly, triggering a range exception if the OVE bit is set in the SR.	jeremybennett	5846d 19h	/openrisc/
113	Updates to exception handling for l.add and l.div	jeremybennett	5847d 18h	/openrisc/
112	Tidy ups to Ethernet test fixes. new tests for l.add. Fixes so l.add computes overflow correctly, and generates a range exception if the the OVE bit is set in the supervision register.	jeremybennett	5847d 18h	/openrisc/
111	Changed conditionals for Verilator to "verilator" instead of "VERILATOR".	jeremybennett	5847d 23h	/openrisc/
110	or1ksim make check should work without a libc in the or32-elf tools	julius	5848d 20h	/openrisc/
109	or_debug_proxy does signals with signals, just ignores signals	julius	5849d 04h	/openrisc/
108	Updated to clarify overflow and exceptions for l.add, l.addc, l.addi, l.addic, l.div and l.divu.	jeremybennett	5850d 18h	/openrisc/
107	New instruction set testing infrastructure. Fix for l.div/li.divu (Bug 1770) and tests for that bug.	jeremybennett	5850d 19h	/openrisc/
106	Removing old tests, pending addition of new ones.	jeremybennett	5850d 19h	/openrisc/