OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] - Rev 450

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
430 or1ksim - clarifying interrupt behavior in code and documentation. julius 5352d 04h /openrisc/
429 or1ksim update - remove debug printfs from eth MDIO emulation function
and fix illegal instruction vector jump for invalid instructions.		 julius 5352d 07h /openrisc/
428 or1ksim - adding preliminary PHY emulation to ethernet peripheral. julius 5355d 03h /openrisc/
427 Fixes for C++ to correspond to fixes in uClibc. jeremybennett 5356d 11h /openrisc/
426 ORPSoC update

Reverted back to previous OR1200 instruction cache.
(...which...)
Fixed or1200-except test failure on generic model.

ML501 build not passing or1200-except test. Tried disabling
burst on the bus (memory server doesn't support it yet) to
no avail. To be continued...		 julius 5357d 22h /openrisc/
425 ORPSoC update:

GDB servers in VPI and System C model updated to deal with
packets gdb-7.2 sends.

Documentation updated.

Reference design tests can now be run in or1ksim (added rule
to sim/bin/Makefile). or1200-except doesn't appear to work
as illegal instruction error isn't causing jump to vector.

Updated Or1200 tests to report test success value and then
exit with value 0.		 julius 5357d 23h /openrisc/
424 C++ library, needed for C++ compiler. jeremybennett 5358d 09h /openrisc/
423 Minor typo fixed. jeremybennett 5358d 12h /openrisc/
422 Separates out --force actions, so only build dirs corresponding to targets being built are blown away. jeremybennett 5358d 12h /openrisc/
421 Fixing some typos in bld-all.sh's --help printout and changed all
"cd .." lines to "cd -".		 julius 5361d 10h /openrisc/

< Prev 1 2

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2025 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.