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Rev Log message Author Age Path
492 ORPSoC VPI interface for modelsim and documentation update julius 5558d 22h /openrisc/
491 ORPSoC or1200_monitor update. julius 5559d 09h /openrisc/
490 Updates to fix spurious test failures and register scheduling. jeremybennett 5563d 15h /openrisc/
489 ORPSoC sw cleanup. Remove warnings. julius 5568d 21h /openrisc/
488 ORPSoC OR1200 driver - tick timer exception handler reverted to generic - cpu tick function hook used as default in handler table. OR1200 timer demo sw for board added. julius 5568d 22h /openrisc/
487 ORPSoC main software makefile update julius 5571d 20h /openrisc/
486 ORPSoC updates, mainly software, i2c driver julius 5571d 20h /openrisc/
485 ORPSoC updates - or1200 monitor now has separate defines file, ethmac updates to fifos and wishbone IF, board.h changes for UART (may propegate to other drivers with multiple cores, we'll see), crt0.S for or1200 now zeros all registers on reset, adding own ethernet tests for ML501 julius 5576d 00h /openrisc/
484 Changes to make r12 call-saved and to bring wchar tests in line. jeremybennett 5576d 22h /openrisc/
483 Updated with new opcodes to generate random numbers and to identify us as Or1ksim. jeremybennett 5579d 00h /openrisc/
482 Don't hardcode tool versions in help text olof 5580d 13h /openrisc/
481 OR1200 Update. RTL and spec. julius 5592d 07h /openrisc/
480 ORPSoC updates - ml501 project cleanups, DDR2 cache bug fixes. julius 5593d 05h /openrisc/
479 ORPSoC update to ml501 board port. Memory controller caching fixed up, does multiple lines of cache and Wishbone bursting. julius 5594d 04h /openrisc/
478 ORPSoC update - ml501 or1200 cache configuration set to maximum, some cleanups. julius 5595d 20h /openrisc/
477 ORPSoC update - Added ability to enable OR1200 caches up to 32KB, which requires line size of 32bytes and 8-beat Wishbone bursts.
Changed cache sizes of both instruction and data cache of reference design to 4kB each.		 julius 5596d 04h /openrisc/
476 ORPSoC updates. Added 16kB cache options to OR1200, now as default on reference design. Cleaned up simulation Makefile more. julius 5596d 21h /openrisc/
475 ORPSoC main simulation makefile tidy up, addition of BSS test to cbasic test, addition or o1ksim config files for each board build, modification of BSS symbols in linker script and crt0. julius 5597d 00h /openrisc/
474 uC/OS-II port linker flags updated. julius 5597d 06h /openrisc/
473 Fix typos in tool chain build script. Add build script for BusyBox/uClibc/Linux. Delete obsolete scripts, improve board description for test, add -pthread flag to GCC for Linux. jeremybennett 5598d 00h /openrisc/

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