URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] - Rev 499

Rev	Log message	Author	Age	Path
479	ORPSoC update to ml501 board port. Memory controller caching fixed up, does multiple lines of cache and Wishbone bursting.	julius	5206d 20h	/openrisc/
478	ORPSoC update - ml501 or1200 cache configuration set to maximum, some cleanups.	julius	5208d 11h	/openrisc/
477	ORPSoC update - Added ability to enable OR1200 caches up to 32KB, which requires line size of 32bytes and 8-beat Wishbone bursts. Changed cache sizes of both instruction and data cache of reference design to 4kB each.	julius	5208d 20h	/openrisc/
476	ORPSoC updates. Added 16kB cache options to OR1200, now as default on reference design. Cleaned up simulation Makefile more.	julius	5209d 13h	/openrisc/
475	ORPSoC main simulation makefile tidy up, addition of BSS test to cbasic test, addition or o1ksim config files for each board build, modification of BSS symbols in linker script and crt0.	julius	5209d 15h	/openrisc/
474	uC/OS-II port linker flags updated.	julius	5209d 21h	/openrisc/
473	Fix typos in tool chain build script. Add build script for BusyBox/uClibc/Linux. Delete obsolete scripts, improve board description for test, add -pthread flag to GCC for Linux.	jeremybennett	5210d 16h	/openrisc/
472	Various changes which improve the quality of the tracing.	jeremybennett	5210d 17h	/openrisc/
471	Adding ucos-ii port.	julius	5212d 20h	/openrisc/
470	ORPSoC OR1200 crt0 updates.	julius	5213d 15h	/openrisc/