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[/] [openrisc/] [trunk/] [or1ksim/] [cpu/] - Rev 224

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224 Add new library functions and modify existing ones. Change the parameter type enumarations to upper case. New (simplified and corrected) config file parsing. No include files or default sim.cfg. jeremybennett 5708d 07h /openrisc/trunk/or1ksim/cpu/
220 Updated library interface to take a full command line (this will break all old code). Added -q/--quiet and --report-memory-errors flags to command line. Fixed all tests to match this. jeremybennett 5714d 23h /openrisc/trunk/or1ksim/cpu/
202 Adding executed log in binary format capability to or1ksim julius 5721d 03h /openrisc/trunk/or1ksim/cpu/
143 Fix building for Cygwin with GCC 3.4.4 (Bug 1797). Fix breakpoints with instruction cache enabled (Bug 195). jeremybennett 5738d 03h /openrisc/trunk/or1ksim/cpu/
127 New config option to allow l.xori with unsigned operand. jeremybennett 5752d 03h /openrisc/trunk/or1ksim/cpu/
124 Overflow handling now in line with architecture manual. Tests added. jeremybennett 5752d 23h /openrisc/trunk/or1ksim/cpu/
123 Implementation of l.mfspr and l.mtspr corrected to use bitwise OR rather than addition. Associated tests added. jeremybennett 5753d 03h /openrisc/trunk/or1ksim/cpu/
122 Added l.ror and l.rori with associated tests. jeremybennett 5753d 23h /openrisc/trunk/or1ksim/cpu/
121 Adds exception handling to l.jalr and l.jr. Adds appropriate tests. jeremybennett 5754d 00h /openrisc/trunk/or1ksim/cpu/
118 New tests of multiply. Improved tests of exception handling for addition and division. Improvements to instruction testing library. jeremybennett 5754d 21h /openrisc/trunk/or1ksim/cpu/
116 Updated to fix l.maci and add tests for l.mac, l.maci, l.macrc and l.msb. Fixed bugs in the old Or1ksim mul test at the same time. jeremybennett 5757d 00h /openrisc/trunk/or1ksim/cpu/
115 Added support for l.fl1 and tests for l.ff1 and l.fl1 jeremybennett 5758d 00h /openrisc/trunk/or1ksim/cpu/
114 l.addic added. Tests of l.add, l.addc, l.addi and l.addic completed. All set overflow correctly, triggering a range exception if the OVE bit is set in the SR. jeremybennett 5758d 01h /openrisc/trunk/or1ksim/cpu/
112 Tidy ups to Ethernet test fixes. new tests for l.add. Fixes so l.add computes overflow correctly, and generates a range exception if the the OVE bit is set in the supervision register. jeremybennett 5758d 23h /openrisc/trunk/or1ksim/cpu/
107 New instruction set testing infrastructure. Fix for l.div/li.divu (Bug 1770) and tests for that bug. jeremybennett 5762d 00h /openrisc/trunk/or1ksim/cpu/
104 Candidate release 0.4.0rc4 jeremybennett 5765d 07h /openrisc/trunk/or1ksim/cpu/
101 ChangeLog updated for floating point support. Fixed bug in generic peripheral upcalls. Upped release date in configure.ac. Removed redundant debugging print in abstract.c jeremybennett 5774d 01h /openrisc/trunk/or1ksim/cpu/
100 Single precision FPU stuff for or1ksim julius 5774d 04h /openrisc/trunk/or1ksim/cpu/
98 Comprehensive testing of the library JTAG interface. Updates to the documentation to warn of issues in using the memory controller. jeremybennett 5780d 03h /openrisc/trunk/or1ksim/cpu/
97 Updates to test the new JTAG library interface (not yet complete). jeremybennett 5794d 09h /openrisc/trunk/or1ksim/cpu/

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