| Rev |
Log message |
Author |
Age |
Path |
| 185 |
Adding single precision FPU to or1200, initial checkin, not fully tested yet |
julius |
5365d 22h |
/openrisc/trunk/orpsocv2/ |
| 111 |
Changed conditionals for Verilator to "verilator" instead of "VERILATOR". |
jeremybennett |
5398d 00h |
/openrisc/trunk/orpsocv2/ |
| 78 |
Fixed typo in Silos workaround script |
rherveille |
5460d 19h |
/openrisc/trunk/orpsocv2/ |
| 77 |
Added support for Silvaco's Silos simulator
Added workaround for Silos's exit code behaviour |
rherveille |
5460d 19h |
/openrisc/trunk/orpsocv2/ |
| 76 |
Added: +libext+.v
Added: +incdir+. |
rherveille |
5461d 19h |
/openrisc/trunk/orpsocv2/ |
| 71 |
ORPSoC board builds, adding readmes |
julius |
5504d 04h |
/openrisc/trunk/orpsocv2/ |
| 70 |
ORPSoC cycle accurate trace generation now compatible with latest version of Verilator \(3.800\) - This will break VCD generation on systems which earlier verilator versions\! |
julius |
5508d 09h |
/openrisc/trunk/orpsocv2/ |
| 69 |
ORPSoC xilinx ml501 board update - added ethernet eupport and software test |
julius |
5508d 10h |
/openrisc/trunk/orpsocv2/ |
| 68 |
Fixed up a couple of Makefile things in ORPSoCv2 |
julius |
5511d 02h |
/openrisc/trunk/orpsocv2/ |
| 67 |
New synthesizable builds of ORPSoC - first for the Xilinx ML501 Virtex 5 board, with working Xilinx MIG DDR2 Controller - added new pad option to bin2vmem, moved spi controller from or1k_startup module to its own directory |
julius |
5511d 04h |
/openrisc/trunk/orpsocv2/ |
| 66 |
Fixed the simulator-assisted printf l.nop in cycle accurate, and supporting software. |
julius |
5531d 03h |
/openrisc/trunk/orpsocv2/ |
| 65 |
ORPSoCv2 update: or1200_defines DVRDCR value, verilog testbench uart decoder fix |
julius |
5535d 09h |
/openrisc/trunk/orpsocv2/ |
| 64 |
Trying to fix the system c model jtagsc.h checkout problem, also removed dependency generation in the system c modules makefile. |
julius |
5538d 04h |
/openrisc/trunk/orpsocv2/ |
| 63 |
Finally adding RSP server to cycle accurate model, based on work by Jeremey Bennett but slightly modified for the debug unit we use. Adding binary logging file mode to cycle accurate model which allows smaller and quicker execution logging, along with binary log reader in sw/utils. Adding cycle accurate wishbone bus transaction log generation. still some bugs in CA model for some reason where it skips cycles when logging either execution or bus transactions. Changing or1200 du allowing hardware watchpoints on data load and stores. |
julius |
5548d 01h |
/openrisc/trunk/orpsocv2/ |
| 58 |
ORPSoC2 update - added fpu and implemented in processor, also some sw tests for it, makefile for event sims cleaned up |
julius |
5589d 21h |
/openrisc/trunk/orpsocv2/ |
| 57 |
ORPSoC execution logs created by event sim and cycle accurate should now be equivalent. Changed some of the rule names in orpsoc main makefile to make all rules use hyphens instead of underscores between words |
julius |
5595d 01h |
/openrisc/trunk/orpsocv2/ |
| 56 |
adding generic pll model to orpsoc |
julius |
5603d 03h |
/openrisc/trunk/orpsocv2/ |
| 55 |
Added modelsim support to makefile. Moved buffer libraries to sensible place. Removed a lot of junk |
julius |
5605d 17h |
/openrisc/trunk/orpsocv2/ |
| 54 |
wb_conbus wishbone arbiter now in orpsocv2 instead of synthesized netlist |
julius |
5616d 00h |
/openrisc/trunk/orpsocv2/ |
| 53 |
Fixed incorrect commandline option for ORPSoC and main makefile setting |
julius |
5634d 01h |
/openrisc/trunk/orpsocv2/ |
| 52 |
ORPSoC update - ability to dump part or all of SRAM contents at the end of simulation |
julius |
5634d 21h |
/openrisc/trunk/orpsocv2/ |
| 51 |
ORPSoCv2 updates: cycle accurate profiling, ELF loading |
julius |
5648d 23h |
/openrisc/trunk/orpsocv2/ |
| 50 |
Adding or32_funcs.S |
julius |
5649d 03h |
/openrisc/trunk/orpsocv2/ |
| 49 |
Lots of ORPSoC Updates. Cycle accurate model update. Enabled block read from CPU via debug interface. SMII interface same as devboard but may be broken in sim now. Makefile update |
julius |
5667d 17h |
/openrisc/trunk/orpsocv2/ |
| 46 |
debug interfaces now support byte and non-aligned accesses from gdb |
julius |
5683d 04h |
/openrisc/trunk/orpsocv2/ |
| 45 |
Orpsoc eth test fix and script error message update |
julius |
5690d 04h |
/openrisc/trunk/orpsocv2/ |
| 44 |
New SystemC model monitoring functions, ethernet PHY model and test sw, smii decoder for ethernet PHY, various makefile upgrades |
julius |
5719d 04h |
/openrisc/trunk/orpsocv2/ |
| 43 |
Couple of fixes to ORPSoC, new linux patch version in toolchain script |
julius |
5743d 01h |
/openrisc/trunk/orpsocv2/ |
| 42 |
Fixed ORPSoCv2 VCD dumping and UART output in cycleaccurate model |
julius |
5758d 21h |
/openrisc/trunk/orpsocv2/ |
| 41 |
Update to or1k top |
julius |
5761d 23h |
/openrisc/trunk/orpsocv2/ |
