URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] - Rev 404

Rev	Log message	Author	Age	Path
351	OR1200 with icarus fixed up. MMu test fix, remove testfloat elf, adding new arbiter and RAM, may break verilator compatibility... TODO	julius	5401d 06h	/openrisc/trunk/orpsocv2/
350	Adding new OR1200 processor to ORPSoCv2	julius	5401d 10h	/openrisc/trunk/orpsocv2/
349	ORPSoCv2 update with new software and makefile update	julius	5401d 10h	/openrisc/trunk/orpsocv2/
348	First stage of ORPSoCv2 update - more to come	julius	5401d 10h	/openrisc/trunk/orpsocv2/
185	Adding single precision FPU to or1200, initial checkin, not fully tested yet	julius	5459d 08h	/openrisc/trunk/orpsocv2/
111	Changed conditionals for Verilator to "verilator" instead of "VERILATOR".	jeremybennett	5491d 10h	/openrisc/trunk/orpsocv2/
78	Fixed typo in Silos workaround script	rherveille	5554d 05h	/openrisc/trunk/orpsocv2/
77	Added support for Silvaco's Silos simulator Added workaround for Silos's exit code behaviour	rherveille	5554d 05h	/openrisc/trunk/orpsocv2/
76	Added: +libext+.v Added: +incdir+.	rherveille	5555d 05h	/openrisc/trunk/orpsocv2/
71	ORPSoC board builds, adding readmes	julius	5597d 15h	/openrisc/trunk/orpsocv2/