| Rev |
Log message |
Author |
Age |
Path |
| 492 |
ORPSoC VPI interface for modelsim and documentation update |
julius |
5560d 20h |
/openrisc/trunk/orpsocv2/ |
| 491 |
ORPSoC or1200_monitor update. |
julius |
5561d 06h |
/openrisc/trunk/orpsocv2/ |
| 489 |
ORPSoC sw cleanup. Remove warnings. |
julius |
5570d 19h |
/openrisc/trunk/orpsocv2/ |
| 488 |
ORPSoC OR1200 driver - tick timer exception handler reverted to generic - cpu tick function hook used as default in handler table. OR1200 timer demo sw for board added. |
julius |
5570d 19h |
/openrisc/trunk/orpsocv2/ |
| 487 |
ORPSoC main software makefile update |
julius |
5573d 17h |
/openrisc/trunk/orpsocv2/ |
| 486 |
ORPSoC updates, mainly software, i2c driver |
julius |
5573d 17h |
/openrisc/trunk/orpsocv2/ |
| 485 |
ORPSoC updates - or1200 monitor now has separate defines file, ethmac updates to fifos and wishbone IF, board.h changes for UART (may propegate to other drivers with multiple cores, we'll see), crt0.S for or1200 now zeros all registers on reset, adding own ethernet tests for ML501 |
julius |
5577d 22h |
/openrisc/trunk/orpsocv2/ |
| 480 |
ORPSoC updates - ml501 project cleanups, DDR2 cache bug fixes. |
julius |
5595d 02h |
/openrisc/trunk/orpsocv2/ |
| 479 |
ORPSoC update to ml501 board port. Memory controller caching fixed up, does multiple lines of cache and Wishbone bursting. |
julius |
5596d 02h |
/openrisc/trunk/orpsocv2/ |
| 478 |
ORPSoC update - ml501 or1200 cache configuration set to maximum, some cleanups. |
julius |
5597d 17h |
/openrisc/trunk/orpsocv2/ |
| 477 |
ORPSoC update - Added ability to enable OR1200 caches up to 32KB, which requires line size of 32bytes and 8-beat Wishbone bursts.
Changed cache sizes of both instruction and data cache of reference design to 4kB each. |
julius |
5598d 02h |
/openrisc/trunk/orpsocv2/ |
| 476 |
ORPSoC updates. Added 16kB cache options to OR1200, now as default on reference design. Cleaned up simulation Makefile more. |
julius |
5598d 19h |
/openrisc/trunk/orpsocv2/ |
| 475 |
ORPSoC main simulation makefile tidy up, addition of BSS test to cbasic test, addition or o1ksim config files for each board build, modification of BSS symbols in linker script and crt0. |
julius |
5598d 21h |
/openrisc/trunk/orpsocv2/ |
| 470 |
ORPSoC OR1200 crt0 updates. |
julius |
5602d 21h |
/openrisc/trunk/orpsocv2/ |
| 468 |
ORPSoC update:
Added USER_ELF and USER_VMEM options to reference design simulation scripts.
Changed use of absolute BOARD_PATH variable to simply BOARD relative to board path
ML501's board.h bootrom default now boot from SPI |
julius |
5603d 22h |
/openrisc/trunk/orpsocv2/ |
| 466 |
ORPSoC updates:
Add new test to determine processor's capabilities.
Fix up typo in example in spiflash app README |
julius |
5605d 02h |
/openrisc/trunk/orpsocv2/ |
| 465 |
ORPSoC SPI flash load Makefile and README updates. |
julius |
5605d 16h |
/openrisc/trunk/orpsocv2/ |
| 462 |
ORPSoC SystemC wrapper updates, monitor output more similar to or1ksim.
RAM models updated. |
julius |
5606d 01h |
/openrisc/trunk/orpsocv2/ |
| 456 |
ORPSoCv2 or1200 - SPRs module format and comment update. Or1200 monitor Verilog now displays report and exit l.nops to stdout by default. |
julius |
5617d 17h |
/openrisc/trunk/orpsocv2/ |
| 449 |
ORPSoC - or1200_monitor.v additions enabling new experimental execution checks.
Replace use of "clean-all" with "distclean" as make rule to clean things. |
julius |
5630d 12h |
/openrisc/trunk/orpsocv2/ |
