| Rev |
Log message |
Author |
Age |
Path |
| 815 |
OR1200 debug unit: prevent deadlock when trap instruction stalls
As per mailing list post <20120925160925.5725e06f@latmask.vernier.se>,
the debug unit could deadlock with the instruction decoder if the trap
instruction is held back by a pipeline stall. This change prevents that.
The problem can be reproduced by placing a breakpoint at an unfavorable
position with instruction cache enabled. In our test, this occurred
with or1200-cbasic when placing a breakpoint at test_bss using gdb, but
this is dependent on such factors as cache parameters and compilation
result. |
yannv |
4489d 08h |
/openrisc/trunk/orpsocv2/ |
| 814 |
orpsoc/or1200: Set correct PC after reset when parameter boot_adr is used
Signed-off-by: Olof Kindgren <olof@opencores.org>
Acked-by: Julius Baxter <juliusbaxter@gmail.com> |
olof |
4504d 01h |
/openrisc/trunk/orpsocv2/ |
| 807 |
ORPSoC: Commit for bug 85 - add DSX support to OR1200.
http://bugzilla.opencores.org/bugzilla4/show_bug.cgi?id=85
Also added software tests, and added these tests to default regression test list |
julius |
4619d 19h |
/openrisc/trunk/orpsocv2/ |
| 805 |
ORPSoC: Fix for bug 90 - EPCR on range exception bug
http://bugzilla.opencores.org/bugzilla4/show_bug.cgi?id=90 |
julius |
4619d 19h |
/openrisc/trunk/orpsocv2/ |
| 803 |
ORPSoC: Fix for bug 91, l.sub not setting overflow flag correctly
http://bugzilla.opencores.org/bugzilla4/show_bug.cgi?id=91 |
julius |
4619d 19h |
/openrisc/trunk/orpsocv2/ |
| 801 |
ORPSoC: Fix bug 88
http://bugzilla.opencores.org/bugzilla4/show_bug.cgi?id=88 |
julius |
4625d 00h |
/openrisc/trunk/orpsocv2/ |
| 794 |
ORPSoC, or1200: split out or1200_fpu_intfloat_conv_except module into own file
Fixes lint warnings. |
julius |
4658d 10h |
/openrisc/trunk/orpsocv2/ |
| 789 |
ORPSoC: Patch from R Diez to make RTL sim report l.nops have equivalent formatting to those from or1ksim
Signed-off-by: R Diez <rdiezmail-openrisc@yahoo.de>
Acked-by: Julius Baxter <juliusbaxter@gmail.com> |
julius |
4682d 23h |
/openrisc/trunk/orpsocv2/ |
| 788 |
or1200: Patch from R Diez to remove l.cust5 signal from a sensitivty list when it's not defined.
Signed-off-by: R Diez <rdiezmail-openrisc@yahoo.de>
Acked-by: Julius Baxter <juliusbaxter@gmail.com> |
julius |
4683d 00h |
/openrisc/trunk/orpsocv2/ |
| 679 |
Allow setting the boot address as an external
parameter. If no parameter is used, the value
from OR1200_BOOT_ADR will be used
Signed-off-by: Olof Kindgren <olof@opencores.org>
Acked-by: Julius Baxter <juliusbaxter@gmail.com> |
olof |
4707d 00h |
/openrisc/trunk/orpsocv2/ |
| 677 |
atlys: add 2-clock synchronizer chain for ddr2_calib_done
The signal ddr2_calib_done signal comes from the ddr2 clock domain,
while wb_req is treating it as if it came from wb_clk domain. As a
result the timing analysis tool assumed a worst case scenario of 5ns
between the two domains and the results were miserable.
While we can argue that this is a multi-cycle path, the fact is that
ddr2_calib_done feeds into multiple logic sinks and can potentially
cause meta-stability issue in the design. The solution is to add a
2-clock meta-stability filter to address both the timing problems and
the meta-stability concern.
Signed-off-by: Jason Zheng <jxzheng@gmail.com>
Signed-off-by: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
Acked-by: Olof Kindgren <olof.kindgren@orsoc.se> |
stekern |
4715d 02h |
/openrisc/trunk/orpsocv2/ |
| 673 |
Multiple 64-bit fixes (mostly sign and size of constants). Fix bug #1. |
yannv |
4782d 04h |
/openrisc/trunk/orpsocv2/ |
| 672 |
ORPSoC: Fix Bug 76 - Incorrect unsigned integer less-than compare with COMP3 option enabled
OR1200 RTL fix and software test added. |
julius |
4785d 20h |
/openrisc/trunk/orpsocv2/ |
| 671 |
ORPSoC: Fix for Bug 75 - or1200-except and or1200-ticksyscall regression tests failing due to change in memory model |
julius |
4785d 20h |
/openrisc/trunk/orpsocv2/ |
| 662 |
minor corrections to clean simulation files |
paknick |
4812d 01h |
/openrisc/trunk/orpsocv2/ |
| 661 |
added makefile for icarus simulation |
paknick |
4812d 01h |
/openrisc/trunk/orpsocv2/ |
| 660 |
updated makefiles for simulation with altera ordb2a-ep4ce22 |
paknick |
4812d 03h |
/openrisc/trunk/orpsocv2/ |
| 656 |
orpsoc: cfi_ctrl software driver fix to allow compilation when it's not used |
julius |
4836d 21h |
/openrisc/trunk/orpsocv2/ |
| 655 |
ORPSoC: add CFI flash controller to ml501, sw driver, tests, app, documentation |
julius |
4836d 22h |
/openrisc/trunk/orpsocv2/ |
| 652 |
Fix make compile.tcl for actel backend |
yannv |
4845d 05h |
/openrisc/trunk/orpsocv2/ |
| 651 |
ORPSoC: The ability to use a free/gimped version of Modelsim was restricted to
the reference build's scripts. This patch adds support for it to the
scripts for the board builds as well.
Signed-off-by: Julius Baxter <julius at opencores.org>
acked-by: Stefan Kristiansson <stefan.kristiansson at saunalahti.fi> |
julius |
4850d 00h |
/openrisc/trunk/orpsocv2/ |
| 650 |
ORPSoC: documentation update to fix explanation of Xilinx environment setup, add section for Atlys board, various cleanups |
julius |
4850d 21h |
/openrisc/trunk/orpsocv2/ |
| 638 |
orpsoc: xilinx: use XILINX env variable
instead of rely on custom environment variables,
use the XILINX variable and instruct the user how to
source the scripts that set it.
Signed-off-by: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi> |
stekern |
4891d 15h |
/openrisc/trunk/orpsocv2/ |
| 634 |
orpsoc: atlys: autoregenerate coregen cores
Instead of keeping binary .ngc files of the coregen
generated cores, use coregen to generate them from the .xco
and .cgp file |
stekern |
4896d 15h |
/openrisc/trunk/orpsocv2/ |
| 633 |
orpsoc: add Digilent Atlys spartan6 board README
Signed-off-by: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi> |
stekern |
4896d 15h |
/openrisc/trunk/orpsocv2/ |
| 632 |
orpsoc: add Digilent Atlys spartan6 board sw include file
Signed-off-by: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi> |
stekern |
4896d 15h |
/openrisc/trunk/orpsocv2/ |
| 631 |
orpsoc: add Digilent Atlys spartan6 board testbench
Signed-off-by: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi> |
stekern |
4896d 15h |
/openrisc/trunk/orpsocv2/ |
| 630 |
orpsoc: add Digilent Atlys spartan6 board backend
Signed-off-by: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi> |
stekern |
4896d 15h |
/openrisc/trunk/orpsocv2/ |
| 629 |
orpsoc: add Digilent Atlys spartan6 board or1ksim configuration
Signed-off-by: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi> |
stekern |
4896d 15h |
/openrisc/trunk/orpsocv2/ |
| 628 |
orpsoc: add Digilent Atlys spartan6 board Makefiles
Signed-off-by: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi> |
stekern |
4896d 15h |
/openrisc/trunk/orpsocv2/ |
