| Rev |
Log message |
Author |
Age |
Path |
| 858 |
orpsoc/tests: Fix or1200-dsxinsn when caches are not present
This test would go into an endless loop when caches are not present. |
stekern |
4282d 19h |
/openrisc/trunk/orpsocv2/ |
| 857 |
orpsocv2: remove reference to r32 in context save/restore |
julius |
4292d 09h |
/openrisc/trunk/orpsocv2/ |
| 854 |
Add OR1200_OR32_LWS define to board specific or1200_defines.v |
stekern |
4389d 05h |
/openrisc/trunk/orpsocv2/ |
| 853 |
Declare pcreg_boot before usage
When things were moved around in rev 813, this error was introduced
Signed-off-by: Olof Kindgren <olof at opencores.org>
acked-by: Julius Baxter <julius at opencores.org> |
olof |
4414d 14h |
/openrisc/trunk/orpsocv2/ |
| 850 |
or1200_genpc: fix ipcu_cycstb_o generation
In some circumstances the CPU is still waiting for the lsu to finish
while in a pre branch state. However, ipcu_cycstb_o is set and the cycle
starts with the wrong address on the iwb bus (the one before the
branched address).
This fixes this issue.
Patch by: Franck Jullien <franck.jullien@gmail.com> |
stekern |
4429d 06h |
/openrisc/trunk/orpsocv2/ |
| 849 |
or1200: Fix for cache bug related to first_{hit|miss}_ack
Under certain circumstances, when first_hit_ack and
first_miss_ack is asserted at the same time, cache data
would wrongly be overwritten with bus data.
Patch by: Matthew Hicks <firefalcon@gmail.com> |
stekern |
4429d 06h |
/openrisc/trunk/orpsocv2/ |
| 848 |
or1200: l.lws support
Using the l.lws instruction doesn't work currently.
It simply skips the instruction. No exception or reaction.
The patch attached simply duplicates the behaviour of
l.lwz for l.lws.
Patch by: Jeppe Græsdal Johansen <jjohan07@student.aau.dk> |
stekern |
4429d 06h |
/openrisc/trunk/orpsocv2/ |
| 815 |
OR1200 debug unit: prevent deadlock when trap instruction stalls
As per mailing list post <20120925160925.5725e06f@latmask.vernier.se>,
the debug unit could deadlock with the instruction decoder if the trap
instruction is held back by a pipeline stall. This change prevents that.
The problem can be reproduced by placing a breakpoint at an unfavorable
position with instruction cache enabled. In our test, this occurred
with or1200-cbasic when placing a breakpoint at test_bss using gdb, but
this is dependent on such factors as cache parameters and compilation
result. |
yannv |
4449d 23h |
/openrisc/trunk/orpsocv2/ |
| 814 |
orpsoc/or1200: Set correct PC after reset when parameter boot_adr is used
Signed-off-by: Olof Kindgren <olof@opencores.org>
Acked-by: Julius Baxter <juliusbaxter@gmail.com> |
olof |
4464d 16h |
/openrisc/trunk/orpsocv2/ |
| 807 |
ORPSoC: Commit for bug 85 - add DSX support to OR1200.
http://bugzilla.opencores.org/bugzilla4/show_bug.cgi?id=85
Also added software tests, and added these tests to default regression test list |
julius |
4580d 10h |
/openrisc/trunk/orpsocv2/ |
| 805 |
ORPSoC: Fix for bug 90 - EPCR on range exception bug
http://bugzilla.opencores.org/bugzilla4/show_bug.cgi?id=90 |
julius |
4580d 10h |
/openrisc/trunk/orpsocv2/ |
| 803 |
ORPSoC: Fix for bug 91, l.sub not setting overflow flag correctly
http://bugzilla.opencores.org/bugzilla4/show_bug.cgi?id=91 |
julius |
4580d 10h |
/openrisc/trunk/orpsocv2/ |
| 801 |
ORPSoC: Fix bug 88
http://bugzilla.opencores.org/bugzilla4/show_bug.cgi?id=88 |
julius |
4585d 15h |
/openrisc/trunk/orpsocv2/ |
| 794 |
ORPSoC, or1200: split out or1200_fpu_intfloat_conv_except module into own file
Fixes lint warnings. |
julius |
4619d 01h |
/openrisc/trunk/orpsocv2/ |
| 789 |
ORPSoC: Patch from R Diez to make RTL sim report l.nops have equivalent formatting to those from or1ksim
Signed-off-by: R Diez <rdiezmail-openrisc@yahoo.de>
Acked-by: Julius Baxter <juliusbaxter@gmail.com> |
julius |
4643d 14h |
/openrisc/trunk/orpsocv2/ |
| 788 |
or1200: Patch from R Diez to remove l.cust5 signal from a sensitivty list when it's not defined.
Signed-off-by: R Diez <rdiezmail-openrisc@yahoo.de>
Acked-by: Julius Baxter <juliusbaxter@gmail.com> |
julius |
4643d 15h |
/openrisc/trunk/orpsocv2/ |
| 679 |
Allow setting the boot address as an external
parameter. If no parameter is used, the value
from OR1200_BOOT_ADR will be used
Signed-off-by: Olof Kindgren <olof@opencores.org>
Acked-by: Julius Baxter <juliusbaxter@gmail.com> |
olof |
4667d 15h |
/openrisc/trunk/orpsocv2/ |
| 677 |
atlys: add 2-clock synchronizer chain for ddr2_calib_done
The signal ddr2_calib_done signal comes from the ddr2 clock domain,
while wb_req is treating it as if it came from wb_clk domain. As a
result the timing analysis tool assumed a worst case scenario of 5ns
between the two domains and the results were miserable.
While we can argue that this is a multi-cycle path, the fact is that
ddr2_calib_done feeds into multiple logic sinks and can potentially
cause meta-stability issue in the design. The solution is to add a
2-clock meta-stability filter to address both the timing problems and
the meta-stability concern.
Signed-off-by: Jason Zheng <jxzheng@gmail.com>
Signed-off-by: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
Acked-by: Olof Kindgren <olof.kindgren@orsoc.se> |
stekern |
4675d 17h |
/openrisc/trunk/orpsocv2/ |
| 673 |
Multiple 64-bit fixes (mostly sign and size of constants). Fix bug #1. |
yannv |
4742d 19h |
/openrisc/trunk/orpsocv2/ |
| 672 |
ORPSoC: Fix Bug 76 - Incorrect unsigned integer less-than compare with COMP3 option enabled
OR1200 RTL fix and software test added. |
julius |
4746d 10h |
/openrisc/trunk/orpsocv2/ |
| 671 |
ORPSoC: Fix for Bug 75 - or1200-except and or1200-ticksyscall regression tests failing due to change in memory model |
julius |
4746d 11h |
/openrisc/trunk/orpsocv2/ |
| 662 |
minor corrections to clean simulation files |
paknick |
4772d 16h |
/openrisc/trunk/orpsocv2/ |
| 661 |
added makefile for icarus simulation |
paknick |
4772d 16h |
/openrisc/trunk/orpsocv2/ |
| 660 |
updated makefiles for simulation with altera ordb2a-ep4ce22 |
paknick |
4772d 18h |
/openrisc/trunk/orpsocv2/ |
| 656 |
orpsoc: cfi_ctrl software driver fix to allow compilation when it's not used |
julius |
4797d 12h |
/openrisc/trunk/orpsocv2/ |
| 655 |
ORPSoC: add CFI flash controller to ml501, sw driver, tests, app, documentation |
julius |
4797d 12h |
/openrisc/trunk/orpsocv2/ |
| 652 |
Fix make compile.tcl for actel backend |
yannv |
4805d 19h |
/openrisc/trunk/orpsocv2/ |
| 651 |
ORPSoC: The ability to use a free/gimped version of Modelsim was restricted to
the reference build's scripts. This patch adds support for it to the
scripts for the board builds as well.
Signed-off-by: Julius Baxter <julius at opencores.org>
acked-by: Stefan Kristiansson <stefan.kristiansson at saunalahti.fi> |
julius |
4810d 15h |
/openrisc/trunk/orpsocv2/ |
| 650 |
ORPSoC: documentation update to fix explanation of Xilinx environment setup, add section for Atlys board, various cleanups |
julius |
4811d 12h |
/openrisc/trunk/orpsocv2/ |
| 638 |
orpsoc: xilinx: use XILINX env variable
instead of rely on custom environment variables,
use the XILINX variable and instruct the user how to
source the scripts that set it.
Signed-off-by: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi> |
stekern |
4852d 06h |
/openrisc/trunk/orpsocv2/ |
