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864 ORPSoC: Merge display_arch_state tasks

or1200-monitor contains the tasks display_arch_state and display_arch_state_except which are almost identical. This patch merges these two tasks into one, with a parameter to specify whether it should print out "(exception)" or not

Signed-off-by: Olof Kindgren <olof@opencores.org>
olof 4153d 14h /openrisc/trunk/orpsocv2/
863 ORPSoC: Add paramers to or1200-monitor for setting name and path of log files

Two small patches in one to make or1200-monitor more useful outside of orpsocv2:
- Setting log path with a parameter allows more flexible directory layout
- if the plusarg "testcase" is set at runtime, this is used to set a unique
prefix for the log files. Plusargs are currently not used in orpsocv2, so if
it is not set, the name falls back to the value of the parameter
TEST_NAME_STRING. The value of the parameter is set to the define
`TEST_NAME_STRING in the test bench top levele to avoid any changes to the
orpsocv2 scripts. With this, we can get rid of `include test-defines in
or1200_monitor.v

Signed-off-by: Olof Kindgren <olof@opencores.org>
olof 4159d 18h /openrisc/trunk/orpsocv2/
862 sysc: avoid using orpsoc internal classes directly

The problem with using the internal classes directly is
that you have to use the internally generated name,
this in itself is perhaps not such a big issue, the issue
is that the internal name changes when the underlaying verilog
design changes.
This works around this by using the classes through the
top module, which is part of the external api.
stekern 4170d 10h /openrisc/trunk/orpsocv2/
861 sysc: include unistd.h

write, read, pipe et al are declared in this, newer gcc will
warn on missing declerations, thus making the build to fail
stekern 4170d 10h /openrisc/trunk/orpsocv2/
860 or1200_monitor.v: Remove trailing whitespace olof 4174d 16h /openrisc/trunk/orpsocv2/
858 orpsoc/tests: Fix or1200-dsxinsn when caches are not present

This test would go into an endless loop when caches are not present.
stekern 4274d 23h /openrisc/trunk/orpsocv2/
857 orpsocv2: remove reference to r32 in context save/restore julius 4284d 13h /openrisc/trunk/orpsocv2/
854 Add OR1200_OR32_LWS define to board specific or1200_defines.v stekern 4381d 09h /openrisc/trunk/orpsocv2/
853 Declare pcreg_boot before usage

When things were moved around in rev 813, this error was introduced

Signed-off-by: Olof Kindgren <olof at opencores.org>
acked-by: Julius Baxter <julius at opencores.org>
olof 4406d 18h /openrisc/trunk/orpsocv2/
850 or1200_genpc: fix ipcu_cycstb_o generation

In some circumstances the CPU is still waiting for the lsu to finish
while in a pre branch state. However, ipcu_cycstb_o is set and the cycle
starts with the wrong address on the iwb bus (the one before the
branched address).

This fixes this issue.

Patch by: Franck Jullien <franck.jullien@gmail.com>
stekern 4421d 09h /openrisc/trunk/orpsocv2/
849 or1200: Fix for cache bug related to first_{hit|miss}_ack

Under certain circumstances, when first_hit_ack and
first_miss_ack is asserted at the same time, cache data
would wrongly be overwritten with bus data.

Patch by: Matthew Hicks <firefalcon@gmail.com>
stekern 4421d 09h /openrisc/trunk/orpsocv2/
848 or1200: l.lws support

Using the l.lws instruction doesn't work currently.
It simply skips the instruction. No exception or reaction.
The patch attached simply duplicates the behaviour of
l.lwz for l.lws.

Patch by: Jeppe Græsdal Johansen <jjohan07@student.aau.dk>
stekern 4421d 09h /openrisc/trunk/orpsocv2/
815 OR1200 debug unit: prevent deadlock when trap instruction stalls

As per mailing list post <20120925160925.5725e06f@latmask.vernier.se>,
the debug unit could deadlock with the instruction decoder if the trap
instruction is held back by a pipeline stall. This change prevents that.

The problem can be reproduced by placing a breakpoint at an unfavorable
position with instruction cache enabled. In our test, this occurred
with or1200-cbasic when placing a breakpoint at test_bss using gdb, but
this is dependent on such factors as cache parameters and compilation
result.
yannv 4442d 03h /openrisc/trunk/orpsocv2/
814 orpsoc/or1200: Set correct PC after reset when parameter boot_adr is used

Signed-off-by: Olof Kindgren <olof@opencores.org>
Acked-by: Julius Baxter <juliusbaxter@gmail.com>
olof 4456d 20h /openrisc/trunk/orpsocv2/
807 ORPSoC: Commit for bug 85 - add DSX support to OR1200.

http://bugzilla.opencores.org/bugzilla4/show_bug.cgi?id=85

Also added software tests, and added these tests to default regression test list
julius 4572d 14h /openrisc/trunk/orpsocv2/
805 ORPSoC: Fix for bug 90 - EPCR on range exception bug

http://bugzilla.opencores.org/bugzilla4/show_bug.cgi?id=90
julius 4572d 14h /openrisc/trunk/orpsocv2/
803 ORPSoC: Fix for bug 91, l.sub not setting overflow flag correctly

http://bugzilla.opencores.org/bugzilla4/show_bug.cgi?id=91
julius 4572d 14h /openrisc/trunk/orpsocv2/
801 ORPSoC: Fix bug 88

http://bugzilla.opencores.org/bugzilla4/show_bug.cgi?id=88
julius 4577d 19h /openrisc/trunk/orpsocv2/
794 ORPSoC, or1200: split out or1200_fpu_intfloat_conv_except module into own file

Fixes lint warnings.
julius 4611d 05h /openrisc/trunk/orpsocv2/
789 ORPSoC: Patch from R Diez to make RTL sim report l.nops have equivalent formatting to those from or1ksim

Signed-off-by: R Diez <rdiezmail-openrisc@yahoo.de>
Acked-by: Julius Baxter <juliusbaxter@gmail.com>
julius 4635d 18h /openrisc/trunk/orpsocv2/
788 or1200: Patch from R Diez to remove l.cust5 signal from a sensitivty list when it's not defined.

Signed-off-by: R Diez <rdiezmail-openrisc@yahoo.de>
Acked-by: Julius Baxter <juliusbaxter@gmail.com>
julius 4635d 19h /openrisc/trunk/orpsocv2/
679 Allow setting the boot address as an external
parameter. If no parameter is used, the value
from OR1200_BOOT_ADR will be used

Signed-off-by: Olof Kindgren <olof@opencores.org>
Acked-by: Julius Baxter <juliusbaxter@gmail.com>
olof 4659d 19h /openrisc/trunk/orpsocv2/
677 atlys: add 2-clock synchronizer chain for ddr2_calib_done

The signal ddr2_calib_done signal comes from the ddr2 clock domain,
while wb_req is treating it as if it came from wb_clk domain. As a
result the timing analysis tool assumed a worst case scenario of 5ns
between the two domains and the results were miserable.

While we can argue that this is a multi-cycle path, the fact is that
ddr2_calib_done feeds into multiple logic sinks and can potentially
cause meta-stability issue in the design. The solution is to add a
2-clock meta-stability filter to address both the timing problems and
the meta-stability concern.

Signed-off-by: Jason Zheng <jxzheng@gmail.com>
Signed-off-by: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
Acked-by: Olof Kindgren <olof.kindgren@orsoc.se>
stekern 4667d 21h /openrisc/trunk/orpsocv2/
673 Multiple 64-bit fixes (mostly sign and size of constants). Fix bug #1. yannv 4734d 23h /openrisc/trunk/orpsocv2/
672 ORPSoC: Fix Bug 76 - Incorrect unsigned integer less-than compare with COMP3 option enabled

OR1200 RTL fix and software test added.
julius 4738d 14h /openrisc/trunk/orpsocv2/
671 ORPSoC: Fix for Bug 75 - or1200-except and or1200-ticksyscall regression tests failing due to change in memory model julius 4738d 15h /openrisc/trunk/orpsocv2/
662 minor corrections to clean simulation files paknick 4764d 20h /openrisc/trunk/orpsocv2/
661 added makefile for icarus simulation paknick 4764d 20h /openrisc/trunk/orpsocv2/
660 updated makefiles for simulation with altera ordb2a-ep4ce22 paknick 4764d 22h /openrisc/trunk/orpsocv2/
656 orpsoc: cfi_ctrl software driver fix to allow compilation when it's not used julius 4789d 16h /openrisc/trunk/orpsocv2/

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