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[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] - Rev 52

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Rev Log message Author Age Path
52 ORPSoC update - ability to dump part or all of SRAM contents at the end of simulation julius 5594d 17h /openrisc/trunk/orpsocv2/bench/
51 ORPSoCv2 updates: cycle accurate profiling, ELF loading julius 5608d 19h /openrisc/trunk/orpsocv2/bench/
49 Lots of ORPSoC Updates. Cycle accurate model update. Enabled block read from CPU via debug interface. SMII interface same as devboard but may be broken in sim now. Makefile update julius 5627d 13h /openrisc/trunk/orpsocv2/bench/
46 debug interfaces now support byte and non-aligned accesses from gdb julius 5643d 00h /openrisc/trunk/orpsocv2/bench/
44 New SystemC model monitoring functions, ethernet PHY model and test sw, smii decoder for ethernet PHY, various makefile upgrades julius 5679d 00h /openrisc/trunk/orpsocv2/bench/
42 Fixed ORPSoCv2 VCD dumping and UART output in cycleaccurate model julius 5718d 17h /openrisc/trunk/orpsocv2/bench/
40 Added GDB server to verilog simulation via VPI and make target to build and run this model julius 5723d 00h /openrisc/trunk/orpsocv2/bench/
6 Checking in ORPSoCv2 julius 5741d 12h /openrisc/trunk/orpsocv2/bench/

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