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Rev Log message Author Age Path
789 ORPSoC: Patch from R Diez to make RTL sim report l.nops have equivalent formatting to those from or1ksim

Signed-off-by: R Diez <rdiezmail-openrisc@yahoo.de>
Acked-by: Julius Baxter <juliusbaxter@gmail.com>
julius 4638d 20h /openrisc/trunk/orpsocv2/bench/
655 ORPSoC: add CFI flash controller to ml501, sw driver, tests, app, documentation julius 4792d 19h /openrisc/trunk/orpsocv2/bench/
500 ORPSoC's System C UART model can now accept input from stdin during simulation to drive consoles etc

ML501 simulation makefile update to allow custom ELFs to be specified
julius 5019d 00h /openrisc/trunk/orpsocv2/bench/
495 ORPSoC adding more accessor functions to Micron SDRAM model. julius 5022d 04h /openrisc/trunk/orpsocv2/bench/
493 ORPSoC VPI JTAG interface, hopefully fix 64-bit machine compile issues. julius 5035d 05h /openrisc/trunk/orpsocv2/bench/
491 ORPSoC or1200_monitor update. julius 5036d 14h /openrisc/trunk/orpsocv2/bench/
485 ORPSoC updates - or1200 monitor now has separate defines file, ethmac updates to fifos and wishbone IF, board.h changes for UART (may propegate to other drivers with multiple cores, we'll see), crt0.S for or1200 now zeros all registers on reset, adding own ethernet tests for ML501 julius 5053d 06h /openrisc/trunk/orpsocv2/bench/
477 ORPSoC update - Added ability to enable OR1200 caches up to 32KB, which requires line size of 32bytes and 8-beat Wishbone bursts.
Changed cache sizes of both instruction and data cache of reference design to 4kB each.
julius 5073d 09h /openrisc/trunk/orpsocv2/bench/
468 ORPSoC update:
Added USER_ELF and USER_VMEM options to reference design simulation scripts.
Changed use of absolute BOARD_PATH variable to simply BOARD relative to board path
ML501's board.h bootrom default now boot from SPI
julius 5079d 06h /openrisc/trunk/orpsocv2/bench/
462 ORPSoC SystemC wrapper updates, monitor output more similar to or1ksim.

RAM models updated.
julius 5081d 08h /openrisc/trunk/orpsocv2/bench/
456 ORPSoCv2 or1200 - SPRs module format and comment update. Or1200 monitor Verilog now displays report and exit l.nops to stdout by default. julius 5093d 01h /openrisc/trunk/orpsocv2/bench/
449 ORPSoC - or1200_monitor.v additions enabling new experimental execution checks.

Replace use of "clean-all" with "distclean" as make rule to clean things.
julius 5105d 20h /openrisc/trunk/orpsocv2/bench/
439 ORPSoC update

Ethernet MAC synthesis issues with Actel Synplify D-2009.12A
Ethernet MAC FIFO synthesis issues with Xilinx XST

Multiply/divide tests for to run on target.

Added third interface to ram_wb module, changed reference design RAM to ram_wb
wrapper. Updated verilog and system C monitor modules accordingly.

Added ability to use ram_wb as internal memory on ML501 design.

Fixed ethernet MAC tests for ML501.
julius 5113d 00h /openrisc/trunk/orpsocv2/bench/
435 ORPSoC updates
OR1200 multiply/MAC/division unit update with serial multiply and
divide options. Full divide not synthesizable yet.
New software tests of multiply and divide functionality.
julius 5119d 15h /openrisc/trunk/orpsocv2/bench/
425 ORPSoC update:

GDB servers in VPI and System C model updated to deal with
packets gdb-7.2 sends.

Documentation updated.

Reference design tests can now be run in or1ksim (added rule
to sim/bin/Makefile). or1200-except doesn't appear to work
as illegal instruction error isn't causing jump to vector.

Updated Or1200 tests to report test success value and then
exit with value 0.
julius 5132d 15h /openrisc/trunk/orpsocv2/bench/
415 ORPSoC - ML501 update, working again.
Documentation update including information on ML501 build
OR1200 updates to do with instruction cache tag signal when
invalidate instruction used.
Added ability to define address to pass to SPI flash when
booting.
Added SPI sw test for board which allows inspection of
data in a flash.
julius 5141d 00h /openrisc/trunk/orpsocv2/bench/
408 ORPSoC update - adding support for ORSoC development board, many changes, documentation update, too. julius 5146d 14h /openrisc/trunk/orpsocv2/bench/
403 ORPSoC big upgrade - intermediate check in. Lots still missing. To come very shortly. julius 5147d 20h /openrisc/trunk/orpsocv2/bench/
397 ORPSoCv2:

doc/ path added, with Texinfo documentation. Still a work in progress.

VPI files updated.

OR1200 l.maci instruction test added. highlighting bug with immediate field for that instruction.

Various cycle accurate model updates. Now uses orpsoc-defines.v (processed C-compat. version) to build.
julius 5150d 01h /openrisc/trunk/orpsocv2/bench/
363 ORPSoC's RTL code fixed to pass linting by Verilator.

ORPSoC's debug interface disabled for now in both RTL and System C top level.

Profiled building of cycle-accurate model now done correctly.
julius 5198d 07h /openrisc/trunk/orpsocv2/bench/

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