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[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [sysc/] - Rev 52

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Rev Log message Author Age Path
52 ORPSoC update - ability to dump part or all of SRAM contents at the end of simulation julius 5597d 09h /openrisc/trunk/orpsocv2/bench/sysc/
51 ORPSoCv2 updates: cycle accurate profiling, ELF loading julius 5611d 11h /openrisc/trunk/orpsocv2/bench/sysc/
49 Lots of ORPSoC Updates. Cycle accurate model update. Enabled block read from CPU via debug interface. SMII interface same as devboard but may be broken in sim now. Makefile update julius 5630d 05h /openrisc/trunk/orpsocv2/bench/sysc/
44 New SystemC model monitoring functions, ethernet PHY model and test sw, smii decoder for ethernet PHY, various makefile upgrades julius 5681d 16h /openrisc/trunk/orpsocv2/bench/sysc/
42 Fixed ORPSoCv2 VCD dumping and UART output in cycleaccurate model julius 5721d 10h /openrisc/trunk/orpsocv2/bench/sysc/
6 Checking in ORPSoCv2 julius 5744d 04h /openrisc/trunk/orpsocv2/bench/sysc/

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