URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [sysc/] [src/] - Rev 52

Rev	Log message	Author	Age	Path
52	ORPSoC update - ability to dump part or all of SRAM contents at the end of simulation	julius	5579d 10h	/openrisc/trunk/orpsocv2/bench/sysc/src/
51	ORPSoCv2 updates: cycle accurate profiling, ELF loading	julius	5593d 12h	/openrisc/trunk/orpsocv2/bench/sysc/src/
49	Lots of ORPSoC Updates. Cycle accurate model update. Enabled block read from CPU via debug interface. SMII interface same as devboard but may be broken in sim now. Makefile update	julius	5612d 06h	/openrisc/trunk/orpsocv2/bench/sysc/src/
44	New SystemC model monitoring functions, ethernet PHY model and test sw, smii decoder for ethernet PHY, various makefile upgrades	julius	5663d 17h	/openrisc/trunk/orpsocv2/bench/sysc/src/
42	Fixed ORPSoCv2 VCD dumping and UART output in cycleaccurate model	julius	5703d 11h	/openrisc/trunk/orpsocv2/bench/sysc/src/
6	Checking in ORPSoCv2	julius	5726d 05h	/openrisc/trunk/orpsocv2/bench/sysc/src/