URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [sysc/] [src/] [Or1200MonitorSC.cpp] - Rev 57

Rev	Log message	Author	Age	Path
57	ORPSoC execution logs created by event sim and cycle accurate should now be equivalent. Changed some of the rule names in orpsoc main makefile to make all rules use hyphens instead of underscores between words	julius	5536d 03h	/openrisc/trunk/orpsocv2/bench/sysc/src/Or1200MonitorSC.cpp
53	Fixed incorrect commandline option for ORPSoC and main makefile setting	julius	5575d 03h	/openrisc/trunk/orpsocv2/bench/sysc/src/Or1200MonitorSC.cpp
52	ORPSoC update - ability to dump part or all of SRAM contents at the end of simulation	julius	5575d 23h	/openrisc/trunk/orpsocv2/bench/sysc/src/Or1200MonitorSC.cpp
51	ORPSoCv2 updates: cycle accurate profiling, ELF loading	julius	5590d 01h	/openrisc/trunk/orpsocv2/bench/sysc/src/Or1200MonitorSC.cpp
49	Lots of ORPSoC Updates. Cycle accurate model update. Enabled block read from CPU via debug interface. SMII interface same as devboard but may be broken in sim now. Makefile update	julius	5608d 19h	/openrisc/trunk/orpsocv2/bench/sysc/src/Or1200MonitorSC.cpp
44	New SystemC model monitoring functions, ethernet PHY model and test sw, smii decoder for ethernet PHY, various makefile upgrades	julius	5660d 06h	/openrisc/trunk/orpsocv2/bench/sysc/src/Or1200MonitorSC.cpp
6	Checking in ORPSoCv2	julius	5722d 18h	/openrisc/trunk/orpsocv2/bench/sysc/src/Or1200MonitorSC.cpp