URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

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[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] - Rev 57

Rev	Log message	Author	Age	Path
57	ORPSoC execution logs created by event sim and cycle accurate should now be equivalent. Changed some of the rule names in orpsoc main makefile to make all rules use hyphens instead of underscores between words	julius	5600d 03h	/openrisc/trunk/orpsocv2/rtl/verilog/
55	Added modelsim support to makefile. Moved buffer libraries to sensible place. Removed a lot of junk	julius	5610d 20h	/openrisc/trunk/orpsocv2/rtl/verilog/
54	wb_conbus wishbone arbiter now in orpsocv2 instead of synthesized netlist	julius	5621d 03h	/openrisc/trunk/orpsocv2/rtl/verilog/
51	ORPSoCv2 updates: cycle accurate profiling, ELF loading	julius	5654d 02h	/openrisc/trunk/orpsocv2/rtl/verilog/
49	Lots of ORPSoC Updates. Cycle accurate model update. Enabled block read from CPU via debug interface. SMII interface same as devboard but may be broken in sim now. Makefile update	julius	5672d 20h	/openrisc/trunk/orpsocv2/rtl/verilog/
46	debug interfaces now support byte and non-aligned accesses from gdb	julius	5688d 07h	/openrisc/trunk/orpsocv2/rtl/verilog/
44	New SystemC model monitoring functions, ethernet PHY model and test sw, smii decoder for ethernet PHY, various makefile upgrades	julius	5724d 06h	/openrisc/trunk/orpsocv2/rtl/verilog/
43	Couple of fixes to ORPSoC, new linux patch version in toolchain script	julius	5748d 03h	/openrisc/trunk/orpsocv2/rtl/verilog/
41	Update to or1k top	julius	5767d 01h	/openrisc/trunk/orpsocv2/rtl/verilog/
6	Checking in ORPSoCv2	julius	5786d 19h	/openrisc/trunk/orpsocv2/rtl/verilog/