| Rev |
Log message |
Author |
Age |
Path |
| 502 |
ORPSoC update - or1200, ethmac Xilinx fifos
or1200 in ORPSoC has carry bit, overflow bit, and range exception added and tested. New software tests in ORPSoC library. Ml501 build had ethmac fifos added, and or1200_defines updated to use these new or1200 features by default |
julius |
5210d 01h |
/openrisc/trunk/orpsocv2/sim/ |
| 500 |
ORPSoC's System C UART model can now accept input from stdin during simulation to drive consoles etc
ML501 simulation makefile update to allow custom ELFs to be specified |
julius |
5211d 05h |
/openrisc/trunk/orpsocv2/sim/ |
| 499 |
ORPSoC OR1200 updates - added l.ext instructions with tests, ammended some MAC bugs, decode stage cleanup |
julius |
5211d 22h |
/openrisc/trunk/orpsocv2/sim/ |
| 485 |
ORPSoC updates - or1200 monitor now has separate defines file, ethmac updates to fifos and wishbone IF, board.h changes for UART (may propegate to other drivers with multiple cores, we'll see), crt0.S for or1200 now zeros all registers on reset, adding own ethernet tests for ML501 |
julius |
5245d 10h |
/openrisc/trunk/orpsocv2/sim/ |
| 476 |
ORPSoC updates. Added 16kB cache options to OR1200, now as default on reference design. Cleaned up simulation Makefile more. |
julius |
5266d 07h |
/openrisc/trunk/orpsocv2/sim/ |
| 475 |
ORPSoC main simulation makefile tidy up, addition of BSS test to cbasic test, addition or o1ksim config files for each board build, modification of BSS symbols in linker script and crt0. |
julius |
5266d 10h |
/openrisc/trunk/orpsocv2/sim/ |
| 468 |
ORPSoC update:
Added USER_ELF and USER_VMEM options to reference design simulation scripts.
Changed use of absolute BOARD_PATH variable to simply BOARD relative to board path
ML501's board.h bootrom default now boot from SPI |
julius |
5271d 11h |
/openrisc/trunk/orpsocv2/sim/ |
| 449 |
ORPSoC - or1200_monitor.v additions enabling new experimental execution checks.
Replace use of "clean-all" with "distclean" as make rule to clean things. |
julius |
5298d 01h |
/openrisc/trunk/orpsocv2/sim/ |
| 435 |
ORPSoC updates
OR1200 multiply/MAC/division unit update with serial multiply and
divide options. Full divide not synthesizable yet.
New software tests of multiply and divide functionality. |
julius |
5311d 20h |
/openrisc/trunk/orpsocv2/sim/ |
| 431 |
Updated and move OR1200 supplementary manual.
or_debug_proxy GDB RSP interface fix.
ORPSoC S/W and makefile updates. |
julius |
5318d 03h |
/openrisc/trunk/orpsocv2/sim/ |
| 425 |
ORPSoC update:
GDB servers in VPI and System C model updated to deal with
packets gdb-7.2 sends.
Documentation updated.
Reference design tests can now be run in or1ksim (added rule
to sim/bin/Makefile). or1200-except doesn't appear to work
as illegal instruction error isn't causing jump to vector.
Updated Or1200 tests to report test success value and then
exit with value 0. |
julius |
5324d 20h |
/openrisc/trunk/orpsocv2/sim/ |
| 411 |
Improved ethmac testbench and software.
Renamed some OR1200 library functions to be more generic.
Fixed bug with versatile_mem_ctrl for Actel board.
Added ability to simulate gatelevel modules alongside RTL modules
in board build. |
julius |
5337d 07h |
/openrisc/trunk/orpsocv2/sim/ |
| 403 |
ORPSoC big upgrade - intermediate check in. Lots still missing. To come very shortly. |
julius |
5340d 01h |
/openrisc/trunk/orpsocv2/sim/ |
| 397 |
ORPSoCv2:
doc/ path added, with Texinfo documentation. Still a work in progress.
VPI files updated.
OR1200 l.maci instruction test added. highlighting bug with immediate field for that instruction.
Various cycle accurate model updates. Now uses orpsoc-defines.v (processed C-compat. version) to build. |
julius |
5342d 06h |
/openrisc/trunk/orpsocv2/sim/ |
| 393 |
ORPSoCv2 software rearrangement in progress. Basic tests should now run again. |
julius |
5345d 06h |
/openrisc/trunk/orpsocv2/sim/ |
| 363 |
ORPSoC's RTL code fixed to pass linting by Verilator.
ORPSoC's debug interface disabled for now in both RTL and System C top level.
Profiled building of cycle-accurate model now done correctly. |
julius |
5390d 12h |
/openrisc/trunk/orpsocv2/sim/ |
| 362 |
ORPSoCv2 verilator building working again. Board build fixes to follow |
julius |
5391d 21h |
/openrisc/trunk/orpsocv2/sim/ |
| 360 |
First checkin of new ORPSoC set up - more to come, all but RTL tests temporarily broken |
julius |
5392d 02h |
/openrisc/trunk/orpsocv2/sim/ |
| 356 |
Added new simple MAC test to ORPSoC test suite:
* orpsocv2/sw/or1200asm/or1200asm-mac.S: Added
Fixed MAC pipeline issue in OR1200
* or1200/rtl/verilog/or1200_mult_mac.v: Made mac_op valid only once per insn.
* orpsocv2/rtl/verilog/components/or1200/or1200_mult_mac.v: ""
* orpsocv2/sw/dhry/dhry.c: Changed final output to be same as ORPmon version
* orpsocv2/sim/bin/Makefile: Added new MAC test to default tests |
julius |
5392d 20h |
/openrisc/trunk/orpsocv2/sim/ |
| 354 |
Fixed ORPSoCv2 Dhrystone test, rewrote timer interrut
* sw/support/crt0.S: Tick timer interrupt to increment variable
now in place instead of calling customisable
interrupt vector handler
Changed all system frequencies in design to 50MHz. |
julius |
5394d 02h |
/openrisc/trunk/orpsocv2/sim/ |
| 351 |
OR1200 with icarus fixed up. MMu test fix, remove testfloat elf, adding new arbiter and RAM, may break verilator compatibility... TODO |
julius |
5395d 02h |
/openrisc/trunk/orpsocv2/sim/ |
| 348 |
First stage of ORPSoCv2 update - more to come |
julius |
5395d 06h |
/openrisc/trunk/orpsocv2/sim/ |
| 78 |
Fixed typo in Silos workaround script |
rherveille |
5548d 01h |
/openrisc/trunk/orpsocv2/sim/ |
| 77 |
Added support for Silvaco's Silos simulator
Added workaround for Silos's exit code behaviour |
rherveille |
5548d 02h |
/openrisc/trunk/orpsocv2/sim/ |
| 76 |
Added: +libext+.v
Added: +incdir+. |
rherveille |
5549d 01h |
/openrisc/trunk/orpsocv2/sim/ |
| 70 |
ORPSoC cycle accurate trace generation now compatible with latest version of Verilator \(3.800\) - This will break VCD generation on systems which earlier verilator versions\! |
julius |
5595d 16h |
/openrisc/trunk/orpsocv2/sim/ |
| 69 |
ORPSoC xilinx ml501 board update - added ethernet eupport and software test |
julius |
5595d 17h |
/openrisc/trunk/orpsocv2/sim/ |
| 68 |
Fixed up a couple of Makefile things in ORPSoCv2 |
julius |
5598d 08h |
/openrisc/trunk/orpsocv2/sim/ |
| 67 |
New synthesizable builds of ORPSoC - first for the Xilinx ML501 Virtex 5 board, with working Xilinx MIG DDR2 Controller - added new pad option to bin2vmem, moved spi controller from or1k_startup module to its own directory |
julius |
5598d 11h |
/openrisc/trunk/orpsocv2/sim/ |
| 66 |
Fixed the simulator-assisted printf l.nop in cycle accurate, and supporting software. |
julius |
5618d 09h |
/openrisc/trunk/orpsocv2/sim/ |
