URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [sim/] - Rev 503

Rev	Log message	Author	Age	Path
351	OR1200 with icarus fixed up. MMu test fix, remove testfloat elf, adding new arbiter and RAM, may break verilator compatibility... TODO	julius	5400d 00h	/openrisc/trunk/orpsocv2/sim/
348	First stage of ORPSoCv2 update - more to come	julius	5400d 05h	/openrisc/trunk/orpsocv2/sim/
78	Fixed typo in Silos workaround script	rherveille	5553d 00h	/openrisc/trunk/orpsocv2/sim/
77	Added support for Silvaco's Silos simulator Added workaround for Silos's exit code behaviour	rherveille	5553d 00h	/openrisc/trunk/orpsocv2/sim/
76	Added: +libext+.v Added: +incdir+.	rherveille	5553d 23h	/openrisc/trunk/orpsocv2/sim/
70	ORPSoC cycle accurate trace generation now compatible with latest version of Verilator \(3.800\) - This will break VCD generation on systems which earlier verilator versions\!	julius	5600d 14h	/openrisc/trunk/orpsocv2/sim/
69	ORPSoC xilinx ml501 board update - added ethernet eupport and software test	julius	5600d 15h	/openrisc/trunk/orpsocv2/sim/
68	Fixed up a couple of Makefile things in ORPSoCv2	julius	5603d 06h	/openrisc/trunk/orpsocv2/sim/
67	New synthesizable builds of ORPSoC - first for the Xilinx ML501 Virtex 5 board, with working Xilinx MIG DDR2 Controller - added new pad option to bin2vmem, moved spi controller from or1k_startup module to its own directory	julius	5603d 09h	/openrisc/trunk/orpsocv2/sim/
66	Fixed the simulator-assisted printf l.nop in cycle accurate, and supporting software.	julius	5623d 07h	/openrisc/trunk/orpsocv2/sim/