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[/] [openrisc/] [trunk/] [orpsocv2/] [sim/] [bin/] - Rev 57

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Rev Log message Author Age Path
57 ORPSoC execution logs created by event sim and cycle accurate should now be equivalent. Changed some of the rule names in orpsoc main makefile to make all rules use hyphens instead of underscores between words julius 6010d 23h /openrisc/trunk/orpsocv2/sim/bin/
55 Added modelsim support to makefile. Moved buffer libraries to sensible place. Removed a lot of junk julius 6021d 15h /openrisc/trunk/orpsocv2/sim/bin/
54 wb_conbus wishbone arbiter now in orpsocv2 instead of synthesized netlist julius 6031d 22h /openrisc/trunk/orpsocv2/sim/bin/
53 Fixed incorrect commandline option for ORPSoC and main makefile setting julius 6049d 23h /openrisc/trunk/orpsocv2/sim/bin/
51 ORPSoCv2 updates: cycle accurate profiling, ELF loading julius 6064d 21h /openrisc/trunk/orpsocv2/sim/bin/
49 Lots of ORPSoC Updates. Cycle accurate model update. Enabled block read from CPU via debug interface. SMII interface same as devboard but may be broken in sim now. Makefile update julius 6083d 15h /openrisc/trunk/orpsocv2/sim/bin/
44 New SystemC model monitoring functions, ethernet PHY model and test sw, smii decoder for ethernet PHY, various makefile upgrades julius 6135d 02h /openrisc/trunk/orpsocv2/sim/bin/
43 Couple of fixes to ORPSoC, new linux patch version in toolchain script julius 6158d 23h /openrisc/trunk/orpsocv2/sim/bin/
42 Fixed ORPSoCv2 VCD dumping and UART output in cycleaccurate model julius 6174d 19h /openrisc/trunk/orpsocv2/sim/bin/
40 Added GDB server to verilog simulation via VPI and make target to build and run this model julius 6179d 02h /openrisc/trunk/orpsocv2/sim/bin/
36 Better clean rule in makefile julius 6193d 03h /openrisc/trunk/orpsocv2/sim/bin/
6 Checking in ORPSoCv2 julius 6197d 14h /openrisc/trunk/orpsocv2/sim/bin/

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