URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] - Rev 71

Rev	Log message	Author	Age	Path
51	ORPSoCv2 updates: cycle accurate profiling, ELF loading	julius	5704d 22h	/
50	Adding or32_funcs.S	julius	5705d 02h	/
49	Lots of ORPSoC Updates. Cycle accurate model update. Enabled block read from CPU via debug interface. SMII interface same as devboard but may be broken in sim now. Makefile update	julius	5723d 16h	/
48	Adds an initialization to keep GCC happy in jp1_ll_read_jp1.	jeremybennett	5723d 19h	/
47	debug proxy speed increase, block transfers possible with cpu aslong as dbg_interface has appropriate change, usb chip reinit function, changed some of the retry code in the usb transfer functions	julius	5733d 03h	/
46	debug interfaces now support byte and non-aligned accesses from gdb	julius	5739d 03h	/
45	Orpsoc eth test fix and script error message update	julius	5746d 03h	/
44	New SystemC model monitoring functions, ethernet PHY model and test sw, smii decoder for ethernet PHY, various makefile upgrades	julius	5775d 02h	/
43	Couple of fixes to ORPSoC, new linux patch version in toolchain script	julius	5799d 00h	/
42	Fixed ORPSoCv2 VCD dumping and UART output in cycleaccurate model	julius	5814d 20h	/