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Rev	Log message	Author	Age	Path
71	ORPSoC board builds, adding readmes	julius	5532d 22h	/
70	ORPSoC cycle accurate trace generation now compatible with latest version of Verilator \(3.800\) - This will break VCD generation on systems which earlier verilator versions\!	julius	5537d 03h	/
69	ORPSoC xilinx ml501 board update - added ethernet eupport and software test	julius	5537d 04h	/
68	Fixed up a couple of Makefile things in ORPSoCv2	julius	5539d 19h	/
67	New synthesizable builds of ORPSoC - first for the Xilinx ML501 Virtex 5 board, with working Xilinx MIG DDR2 Controller - added new pad option to bin2vmem, moved spi controller from or1k_startup module to its own directory	julius	5539d 22h	/
66	Fixed the simulator-assisted printf l.nop in cycle accurate, and supporting software.	julius	5559d 20h	/
65	ORPSoCv2 update: or1200_defines DVRDCR value, verilog testbench uart decoder fix	julius	5564d 02h	/
64	Trying to fix the system c model jtagsc.h checkout problem, also removed dependency generation in the system c modules makefile.	julius	5566d 21h	/
63	Finally adding RSP server to cycle accurate model, based on work by Jeremey Bennett but slightly modified for the debug unit we use. Adding binary logging file mode to cycle accurate model which allows smaller and quicker execution logging, along with binary log reader in sw/utils. Adding cycle accurate wishbone bus transaction log generation. still some bugs in CA model for some reason where it skips cycles when logging either execution or bus transactions. Changing or1200 du allowing hardware watchpoints on data load and stores.	julius	5576d 19h	/
62	This material is part of the separate website downloads directory.	jeremybennett	5587d 22h	/
61	The build directory should not be part of the SVN configuration.	jeremybennett	5587d 22h	/
60	Mark Jarvin's patches to support Mac OS X (Snow Leopard).	jeremybennett	5594d 15h	/
59	Toolchain install script gcc patch change and gdb configure change	julius	5615d 16h	/
58	ORPSoC2 update - added fpu and implemented in processor, also some sw tests for it, makefile for event sims cleaned up	julius	5618d 14h	/
57	ORPSoC execution logs created by event sim and cycle accurate should now be equivalent. Changed some of the rule names in orpsoc main makefile to make all rules use hyphens instead of underscores between words	julius	5623d 18h	/
56	adding generic pll model to orpsoc	julius	5631d 20h	/
55	Added modelsim support to makefile. Moved buffer libraries to sensible place. Removed a lot of junk	julius	5634d 11h	/
54	wb_conbus wishbone arbiter now in orpsocv2 instead of synthesized netlist	julius	5644d 18h	/
53	Fixed incorrect commandline option for ORPSoC and main makefile setting	julius	5662d 18h	/
52	ORPSoC update - ability to dump part or all of SRAM contents at the end of simulation	julius	5663d 15h	/

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