OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] - Rev 348

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
348 First stage of ORPSoCv2 update - more to come julius 5209d 09h /
347 Tagging the 0.5.0rc1 candidate release of Or1ksim. jeremybennett 5209d 10h /
346 Changes to support Or1ksim 0.5.0rc1

Top level changes:

* config.h.in: Regenerated.
* debug.cfg, rsp.cfg: Deleted.
* doc/or1ksim.texi: Updated for new options and library interface.
* doc/or1ksim.info, doc/version.texi: Regenerated.
* Makefile.am: Added sim.cfg to EXTRA_DIST.
* NEWS: Updated for 0.5.0rc1.
* or1ksim.h <enum or1ksim_rc>: OR1KSIM_RC_OK explicitly zero.
* sim.cfg: Updated for consistency with the user guide.
* sim-config.c (init_defconfig): 50000 as default VAPI port.
(alloc_memory_block): Verbose message of amount allocated.
* configure: Regenerated.
* configure.ac: Version changed to 0.5.0rc1.

Changes in testsuite:

* libsim.tests/int-edge.exp <int-edge simple 1>: Increase time
between interrupts to 2ms.
<int-edge simple 2>: Increase time between interrupts to 2ms.
<int-edge duplicated 1>: Increase time between interrupts to 2ms.
<int-edge duplicated 2>: Increase time between interrupts to 2ms.

Changes in testsuite/test-code-or1k:

* mc-common/except-mc.S: Remove leading underscores from global
symbols.
* except/except.S: Remove leading underscores from global symbols.
* cache/cache-asm.S: Remove leading underscores from global symbols.
* cache/cache.c (jump_and_link): Remove leading underscore from
label.
(jump): Remove leading underscore from label.
(all): Remove leading underscore from global symbol references.
* testfloat/systfloat.S: Remove leading underscores from global
symbols.
* mmu/mmu.c (jump): Remove leading underscore from label.
* mmu/mmu-asm.S: Remove leading underscores from global symbols.
* except-test/except-test.c: Remove leading underscores from
global symbols.
* except-test/except-test-s.S: Remove leading underscores from
global symbols.
* uos/except-or32.S: Remove leading underscores from global
symbols.
* configure: Regenerated.
* configure.ac: Version changed to 0.5.0rc1.		 jeremybennett 5209d 11h /
345 Tagging the 1.0rc1 candidate release of Newlib 1.18.0 jeremybennett 5210d 06h /
344 Directory for tagging newlib 1.18.0 jeremybennett 5210d 06h /
343 Build C++ and its libraries. jeremybennett 5210d 07h /
342 Various files regenerated as part of RC1 creation. jeremybennett 5210d 07h /
341 Tagging the 1.0rc1 candidate release of GDB 7.2 jeremybennett 5210d 09h /
340 Tag directory for GDB 7.2. jeremybennett 5210d 09h /
339 Updates for GDB 7.2 for OpenRISC version 1.0 release candidate 1. OpenRISC
documentation subsumes the old separate OpenRISC document.		 jeremybennett 5210d 12h /
338 Tagging the 1.0rc1 candidate release of GCC 4.5.1 jeremybennett 5211d 05h /
337 Directory for GCC 4.5.1 tags jeremybennett 5211d 05h /
336 Corrected for 4.5.1-or32-1.0rc1 jeremybennett 5211d 05h /
335 Updated version number to 4.5.1-or32-1.0. jeremybennett 5211d 05h /
334 Record changes to the documentation and option handling. jeremybennett 5211d 05h /
333 Fix the default option (to use -mhard-mul). Update the documentation for
OpenRISC.		 jeremybennett 5211d 06h /
332 Provide support for nested functions. Tidy up board specification.

* config/or32/or32-protos.c <or32_trampoline_code_size>: Added.
* config/or32/or32.c <OR32_MOVHI, OR32_ORI, OR32_LWZ, OR32_JR>:
New macros added.
(or32_emit_mode, or32_emit_binary, or32_force_binary)
(or32_trampoline_code_size, or32_trampoline_init): Created.
(or32_output_bf): Tabbing fixed.
<TARGET_TRAMPOLINE_INIT>: Definition added.
* config/or32/or32.h <STATIC_CHAIN_REGNUM>: Uses R11.
<TRAMPOLINE_SIZE>: redefined.
<TRAMPOLINE_ENVIRONMENT>: Added definition.		 jeremybennett 5212d 05h /
331 Updated for GDB 7.2 and GCC 4.5.1 (which needs target-libgcc). jeremybennett 5212d 13h /
330 Baseline port of GDB 7.2 for OpenRISC 1000 jeremybennett 5213d 00h /
329 Baseline GCC 4.5.1 port for the OpenRISC 1000 jeremybennett 5213d 01h /

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.