OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] - Rev 800

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
800 FreeRTOSV6.1.1
add or32_dma demo task for test dcache manuplation function
add simple driver of wb_dma		 filepang 4581d 11h /
799 FreeRTOSV6.1.1
add cache related function from u-boot from OpenRISC
enable I/D cache if present		 filepang 4582d 11h /
798 Added drivers for ethmac and sdcard_mass_storage_controller skrzyp 4584d 20h /
797 testsuite: kill test processes that timeout pgavin 4593d 01h /
796 Correct orpmon show_rx_buffs and show_mac_regs to use TX_BD_NUM properly. yannv 4596d 04h /
795 Created or1200_rel3 branch from rev 794 olof 4596d 19h /
794 ORPSoC, or1200: split out or1200_fpu_intfloat_conv_except module into own file

Fixes lint warnings.		 julius 4602d 05h /
793 Corrected Julius Baxter's email address in MAINTAINERS jeremybennett 4613d 04h /
792 Added a MAINTAINERS file.

012-04-07 Jeremy Bennett <jeremy.bennett@embecosm.com>

* MAINTAINERS: Added.
* configure: Regenerated.
* configure.ac: Updated version.		 jeremybennett 4613d 04h /
791 Added options to configure RAM and ROM sizes. Fixed cache handling. skrzyp 4615d 23h /
790 fixed issues with context switching, interrupts, optimizations and cleanups skrzyp 4622d 23h /
789 ORPSoC: Patch from R Diez to make RTL sim report l.nops have equivalent formatting to those from or1ksim

Signed-off-by: R Diez <rdiezmail-openrisc@yahoo.de>
Acked-by: Julius Baxter <juliusbaxter@gmail.com>		 julius 4626d 19h /
788 or1200: Patch from R Diez to remove l.cust5 signal from a sensitivty list when it's not defined.

Signed-off-by: R Diez <rdiezmail-openrisc@yahoo.de>
Acked-by: Julius Baxter <juliusbaxter@gmail.com>		 julius 4626d 19h /
787 Patch from R Diez to zero R0 on startup. ChangeLog from testsuite/test-code-or1k:

2012-03-23 Jeremy Bennett <jeremy.bennett@embecosm.com>

Patch from R Diez <rdiezmail-openrisc@yahoo.de>

* cache/cache-asm.S, cfg/cfg.S, except-test/except-test-s.S,
* except/except.S, ext/ext.S, flag/flag.S, fp/fp.S,
* inst-set-test/inst-set-test.S, int-test/int-test.S,
* mc-common/except-mc.S, uos/except-or32.S: Clear R0 on
start-up. There is no guarantee that R0 is hardwired to zero, and
indeed it is not when simulating the or1200 Verilog core.
* configure: Regenerated.
* configure.ac: Updated version.		 jeremybennett 4628d 03h /
786 new ecos tree (tracking mainline) skrzyp 4628d 03h /
785 We are about to upload a new tree (that has a different structure) skrzyp 4628d 04h /
784 Patch from R Diez to ensure DejaGnu handles errors better. Autoconf infrastructure all updated.

2012-03-21 Jeremy Bennett <jeremy.bennett@embecosm.com>

Patch from R Diez <rdiezmail-openrisc@yahoo.de>

* Makefile.am: Add AM_RUNTESTFLAGS to trigger correct error
behaviour.		 jeremybennett 4629d 18h /
783 Initial dev directory snapshot with FSF GCC mainline jeremybennett 4643d 17h /
782 Tags directory for GNU development tool chain. jeremybennett 4643d 17h /
781 Initial check-in of GCC, with properties matching the upstream. jeremybennett 4646d 04h /

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.