OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [rel_29/] - Rev 1765

Rev

Filtering Options

Clear current filter

Rev Log message Author Age Path
1765 root 5519d 04h /or1k/tags/rel_29/
1340 This commit was manufactured by cvs2svn to create tag 'rel_29'. 7036d 16h /tags/rel_29/
1339 revert to the old l.sfxxi behavior phoenix 7036d 16h /trunk/
1338 l.ff1 instruction added andreje 7038d 11h /trunk/
1337 du_hwbkpt disabled when debug unit not implemented andreje 7042d 17h /trunk/
1336 sign/zero extension for l.sfxxi instructions corrected andreje 7042d 17h /trunk/
1335 flag for l.cmov instruction added andreje 7042d 17h /trunk/
1334 l.ff1 and l.cmov instructions added andreje 7042d 17h /trunk/
1333 gcc 3.4 compile fix phoenix 7053d 12h /trunk/
1332 gcc 3.4.3 compile fix phoenix 7057d 06h /trunk/
1331 jtag bugfix phoenix 7062d 05h /trunk/
1330 jtag bugfix phoenix 7062d 06h /trunk/
1329 Synplify synthesis script first import jcastillo 7066d 16h /trunk/
1327 Firt import of OR1200 over Celoxica RC203 platform jcastillo 7067d 10h /trunk/
1325 Initial import of uClibc-0.9.26 phoenix 7098d 04h /trunk/
1324 memory access functions fixes phoenix 7120d 04h /trunk/
1323 Adrian Wise: or1ksim bugfix & Solaris build phoenix 7121d 11h /trunk/
1322 Christian Krauses bugfixes phoenix 7122d 13h /trunk/
1321 some tests rely on exit(0) as a last std output text to pass phoenix 7124d 04h /trunk/
1320 cpu/sim memory accesses separation, tick, exception, nr. of operands, cycles count,... corrections. phoenix 7126d 04h /trunk/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.