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[/] [rs232_interface/] [trunk/] [uart.vhd] - Rev 18

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18 Added RX state verification for start bit process.
Added loop in the parallel interface of TB.
akram.mashni 4286d 12h /rs232_interface/trunk/uart.vhd
11 Moved debouncer to a new process.
Fixed rx_clk_en generation.
Fixed start of reception condition on rx FSM.
akram.mashni 4821d 08h /rs232_interface/trunk/uart.vhd
10 Implemented asynchronous mode and RX clock regeneration.
NOT TESTED !!!
akram.mashni 4829d 02h /rs232_interface/trunk/uart.vhd
7 Implemented PARITY (not tested!). akram.mashni 4868d 04h /rs232_interface/trunk/uart.vhd
6 Fixed/improved header.
Changed SPACEs to TABs.
akram.mashni 4869d 09h /rs232_interface/trunk/uart.vhd
5 Added comments to port map. akram.mashni 4876d 14h /rs232_interface/trunk/uart.vhd
3 Added main file.
Fisrt commit.
Tested in the following conditions:
- Baud rate: 9600 bps.
- Implementation: Xilinx Spartan3e500 (Nexys2 Kit - Digilent)
- Main clock 50 MHz
akram.mashni 4876d 15h /rs232_interface/trunk/uart.vhd

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