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[/] [s1_core/] [trunk/] [hdl/] - Rev 90

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Rev Log message Author Age Path
90 Added newer files from OpenSPARC T1 1.6 preprocessed with "update_sparccore -ee" fafa1971 5916d 17h /s1_core/trunk/hdl/
89 Removed files originated from OpenSPARC T1 Design 1.5 preprocessed with "update_sparccore -me" fafa1971 5916d 17h /s1_core/trunk/hdl/
82 DC synthesis script modified according to the fabolous manual (RTFM...). fafa1971 6078d 00h /s1_core/trunk/hdl/
81 Sorry, I made a mistake in the waveform of the clock! fafa1971 6078d 04h /s1_core/trunk/hdl/
79 Relaxed timing, added flatten and hyerarchical report_area. fafa1971 6081d 00h /s1_core/trunk/hdl/
75 Changed preprocessing for DC synthesis fafa1971 6181d 01h /s1_core/trunk/hdl/
74 Updated filelists. fafa1971 6181d 01h /s1_core/trunk/hdl/
73 New version of scripts for DC and to compile boot code fafa1971 6181d 01h /s1_core/trunk/hdl/
58 These were only symbolic links to remember where such these things were defined fafa1971 6243d 16h /s1_core/trunk/hdl/
57 Latest version fafa1971 6243d 16h /s1_core/trunk/hdl/
56 Updated from OpenSPARC T1 version 1.4 to version 1.5 fafa1971 6243d 16h /s1_core/trunk/hdl/
55 Nobody remembers why these blackboxed files were required! fafa1971 6243d 16h /s1_core/trunk/hdl/
54 Updated filelists fafa1971 6243d 16h /s1_core/trunk/hdl/
53 Removed from CVS tree because header file preprocessing is done elsewhere fafa1971 6243d 17h /s1_core/trunk/hdl/
52 Updated SPARC Core files from OpenSPARC T1 version 1.4 to version 1.5 fafa1971 6243d 17h /s1_core/trunk/hdl/
51 User Chris "gaterocket" corrected a couple of errors for FPGA boards: blocking assignments and two uninitialized variables. fafa1971 6329d 17h /s1_core/trunk/hdl/
48 Updated with new OpenSPARC 1.4 list fafa1971 6394d 15h /s1_core/trunk/hdl/
46 Fresh version from OpenSPARC 1.4 and Icarus define preprocessing fafa1971 6394d 15h /s1_core/trunk/hdl/
45 I'm going to remove original OpenSPARC 1.4 files so that I can insert again
the ones with Icarus Verilog preprocessor already applied by update_sparccore
(it seems that Xilinx's XST does NOT support defines at compile time)		 fafa1971 6394d 15h /s1_core/trunk/hdl/
44 Embedded `defines into Verilog source since did not find command line option for XST fafa1971 6395d 14h /s1_core/trunk/hdl/

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