URL https://opencores.org/ocsvn/s1_core/s1_core/trunk

Subversion Repositories s1_core

[/] [s1_core/] [trunk/] [hdl/] - Rev 98

Rev	Log message	Author	Age	Path
51	User Chris "gaterocket" corrected a couple of errors for FPGA boards: blocking assignments and two uninitialized variables.	fafa1971	6425d 07h	/s1_core/trunk/hdl/
48	Updated with new OpenSPARC 1.4 list	fafa1971	6490d 06h	/s1_core/trunk/hdl/
46	Fresh version from OpenSPARC 1.4 and Icarus define preprocessing	fafa1971	6490d 06h	/s1_core/trunk/hdl/
45	I'm going to remove original OpenSPARC 1.4 files so that I can insert again the ones with Icarus Verilog preprocessor already applied by update_sparccore (it seems that Xilinx's XST does NOT support defines at compile time)	fafa1971	6490d 06h	/s1_core/trunk/hdl/
44	Embedded `defines into Verilog source since did not find command line option for XST	fafa1971	6491d 04h	/s1_core/trunk/hdl/
39	Empty modules for cacheless Simply RISC S1 Core	fafa1971	6491d 04h	/s1_core/trunk/hdl/
25	Updated filelists according to the new OpenSPARC 1.4, and add some minor changes like Stephen Williams's suggestion to use $(S1_ROOT) in the filelists for Icarus Verilog (he's the author!).	fafa1971	6505d 07h	/s1_core/trunk/hdl/
24	Fresh files taken from most recent OpenSPARC 1.4.	fafa1971	6505d 07h	/s1_core/trunk/hdl/
23	Fresh file taken from the most recent OpenSPARC 1.4.	fafa1971	6505d 07h	/s1_core/trunk/hdl/
22	Removed files of OpenSPARC 1.3 to later add the 1.4 ones.	fafa1971	6505d 07h	/s1_core/trunk/hdl/