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14 Modified the loader so that it will load even if there are RAM variables
in the load, just as long as they aren't anything but zero. (The startup code,
however, doesn't clear memory to match--so be sure to initialize all variables.)
dgisselq 2769d 15h /
13 Fixed a nasty parameter problem between toplevel and txuart. The UART
transmitter now both works (again), and properly generates the required
interrupts. This also finishes the fixes to the alternate toplevel file,
alttop.v, that should've been fixed in the last release.
dgisselq 2769d 16h /
12 The UART and PWM audio now work. This includes the changes to make that
happen, as well as the source code for some UART and PWM demo programs.
dgisselq 2770d 13h /
11 Runs on hardware now! Added proper pinouts, pipelined wishbone command
interface sufficient for loading the flash, a loader to load the flash,
and verified that they work.
dgisselq 2771d 11h /
10 Added the capability to run ELF files natively, fully processing the ELF format. dgisselq 2771d 11h /
9 Added pinout diagrams, based upon a (hopefully) final UCF file. dgisselq 2771d 11h /
8 First pseudo-running version. The alternate configuration (not the main one)
has been initially tested. wbregs works for reading/writing registers,
so it is now possible to test the peripherals.
dgisselq 2776d 12h /
7 Created/added an initial specification. Updated/corrected several copywrite
notices.
dgisselq 2777d 03h /
6 Initial UCF modifications. Pin layout still isn't complete, but I'm starting
to work it.
dgisselq 2797d 22h /
5 These two are my first attempt(s) at a secondary project file, one that can
run as an alternate to the main file but that gives more access to the hardware,
such as programming access to the flash.
dgisselq 2797d 22h /
4 Lots of updates, as part of actually making this work on hardware. Not there
yet, so this is still pre-alpha.
dgisselq 2797d 22h /
3 Updated date. dgisselq 2797d 22h /
2 The initial check in--all the files that will make this SoC work. dgisselq 2808d 17h /
1 The project and the structure was created root 2808d 18h /

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