OpenCores
URL https://opencores.org/ocsvn/s6soc/s6soc/trunk

Subversion Repositories s6soc

[/] [s6soc/] - Rev 12

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
12 The UART and PWM audio now work. This includes the changes to make that
happen, as well as the source code for some UART and PWM demo programs.		 dgisselq 2916d 14h /s6soc/
11 Runs on hardware now! Added proper pinouts, pipelined wishbone command
interface sufficient for loading the flash, a loader to load the flash,
and verified that they work.		 dgisselq 2917d 12h /s6soc/
10 Added the capability to run ELF files natively, fully processing the ELF format. dgisselq 2917d 12h /s6soc/
9 Added pinout diagrams, based upon a (hopefully) final UCF file. dgisselq 2917d 12h /s6soc/
8 First pseudo-running version. The alternate configuration (not the main one)
has been initially tested. wbregs works for reading/writing registers,
so it is now possible to test the peripherals.		 dgisselq 2922d 13h /s6soc/
7 Created/added an initial specification. Updated/corrected several copywrite
notices.		 dgisselq 2923d 04h /s6soc/
6 Initial UCF modifications. Pin layout still isn't complete, but I'm starting
to work it.		 dgisselq 2943d 23h /s6soc/
5 These two are my first attempt(s) at a secondary project file, one that can
run as an alternate to the main file but that gives more access to the hardware,
such as programming access to the flash.		 dgisselq 2943d 23h /s6soc/
4 Lots of updates, as part of actually making this work on hardware. Not there
yet, so this is still pre-alpha.		 dgisselq 2943d 23h /s6soc/
3 Updated date. dgisselq 2943d 23h /s6soc/
2 The initial check in--all the files that will make this SoC work. dgisselq 2954d 18h /s6soc/
1 The project and the structure was created root 2954d 19h /s6soc/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.