OpenCores

URL https://opencores.org/ocsvn/s6soc/s6soc/trunk

Subversion Repositories s6soc

[/] [s6soc/] [trunk/] - Rev 12

Go to most recent revision

Filtering Options

Rev	Log message	Author	Age	Path
12	The UART and PWM audio now work. This includes the changes to make that happen, as well as the source code for some UART and PWM demo programs.	dgisselq	2917d 01h	/s6soc/trunk/
11	Runs on hardware now! Added proper pinouts, pipelined wishbone command interface sufficient for loading the flash, a loader to load the flash, and verified that they work.	dgisselq	2917d 23h	/s6soc/trunk/
10	Added the capability to run ELF files natively, fully processing the ELF format.	dgisselq	2917d 23h	/s6soc/trunk/
9	Added pinout diagrams, based upon a (hopefully) final UCF file.	dgisselq	2917d 23h	/s6soc/trunk/
8	First pseudo-running version. The alternate configuration (not the main one) has been initially tested. wbregs works for reading/writing registers, so it is now possible to test the peripherals.	dgisselq	2923d 00h	/s6soc/trunk/
7	Created/added an initial specification. Updated/corrected several copywrite notices.	dgisselq	2923d 14h	/s6soc/trunk/
6	Initial UCF modifications. Pin layout still isn't complete, but I'm starting to work it.	dgisselq	2944d 09h	/s6soc/trunk/
5	These two are my first attempt(s) at a secondary project file, one that can run as an alternate to the main file but that gives more access to the hardware, such as programming access to the flash.	dgisselq	2944d 09h	/s6soc/trunk/
4	Lots of updates, as part of actually making this work on hardware. Not there yet, so this is still pre-alpha.	dgisselq	2944d 09h	/s6soc/trunk/
3	Updated date.	dgisselq	2944d 09h	/s6soc/trunk/
2	The initial check in--all the files that will make this SoC work.	dgisselq	2955d 04h	/s6soc/trunk/
1	The project and the structure was created	root	2955d 06h	/s6soc/trunk/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.