URL https://opencores.org/ocsvn/s6soc/s6soc/trunk

Subversion Repositories s6soc

[/] [s6soc/] [trunk/] [rtl/] [cpu/] - Rev 12

Rev	Log message	Author	Age	Path
11	Runs on hardware now! Added proper pinouts, pipelined wishbone command interface sufficient for loading the flash, a loader to load the flash, and verified that they work.	dgisselq	2918d 05h	/s6soc/trunk/rtl/cpu/
8	First pseudo-running version. The alternate configuration (not the main one) has been initially tested. wbregs works for reading/writing registers, so it is now possible to test the peripherals.	dgisselq	2923d 05h	/s6soc/trunk/rtl/cpu/
7	Created/added an initial specification. Updated/corrected several copywrite notices.	dgisselq	2923d 20h	/s6soc/trunk/rtl/cpu/
4	Lots of updates, as part of actually making this work on hardware. Not there yet, so this is still pre-alpha.	dgisselq	2944d 15h	/s6soc/trunk/rtl/cpu/
2	The initial check in--all the files that will make this SoC work.	dgisselq	2955d 10h	/s6soc/trunk/rtl/cpu/