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[/] [s6soc/] [trunk/] [rtl/] [cpu/] [zipcpu.v] - Rev 51

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Rev Log message Author Age Path
51 Latest RTL changes, adding 20 cycles/instruction to CPU dgisselq 2140d 14h /s6soc/trunk/rtl/cpu/zipcpu.v
46 Added missing files from the 8b branch, deleted unneeded files dgisselq 2159d 15h /s6soc/trunk/rtl/cpu/zipcpu.v
30 Brings the CPU up to date with the rest of the ZipCPU distribution. dgisselq 2458d 04h /s6soc/trunk/rtl/cpu/zipcpu.v
23 Fixed a bug which caused every instruction to be loaded/prefetched twice. dgisselq 2462d 15h /s6soc/trunk/rtl/cpu/zipcpu.v
16 Bug fix. This release fixes several bugs associated with transitioning from
user mode to supervisor mode while running from flash memory. This also
rewires TIMER-B into a watch-dog timer, and adjusts the LED's to be an
indicator of interrupts and whether or not the CPU has stalled or not as well.
dgisselq 2466d 14h /s6soc/trunk/rtl/cpu/zipcpu.v
11 Runs on hardware now! Added proper pinouts, pipelined wishbone command
interface sufficient for loading the flash, a loader to load the flash,
and verified that they work.
dgisselq 2474d 04h /s6soc/trunk/rtl/cpu/zipcpu.v
7 Created/added an initial specification. Updated/corrected several copywrite
notices.
dgisselq 2479d 19h /s6soc/trunk/rtl/cpu/zipcpu.v
2 The initial check in--all the files that will make this SoC work. dgisselq 2511d 09h /s6soc/trunk/rtl/cpu/zipcpu.v

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