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Rev Log message Author Age Path
41 Updated Spec ver 0.1 is added back to svn dinesha 4261d 23h /
40 Application layer Fifo full conditional are register now to synth timing fixes dinesha 4262d 16h /
39 Test Bench upgradation with bigger data burst size dinesha 4262d 16h /
38 Port Name clean up dinesha 4263d 21h /
37 SDRAM dq and sdram pad clock are termindated inside the top rtl files dinesha 4263d 23h /
36 Clean up dinesha 4264d 14h /
35 Updated the New Documents - ver 0.1 dinesha 4264d 15h /
34 Removed the older version dinesha 4264d 15h /
33 clean up dinesha 4264d 16h /
32 Debug is enable through +define dinesha 4266d 15h /
31 Integrated SDRAM controller with wishbone interface is added into SVN dinesha 4266d 15h /
30 test bench file for integrated SDRAM controller with wish bone and Standalone SDRAM controller test bench are added into SVN dinesha 4266d 15h /
29 SDRAM top and core related run file list are added into svn dinesha 4266d 15h /
28 SDRAM top and SDRAM Core Golden files are added into SVN dinesha 4266d 15h /
27 Golden log file corresponds the SDRAM core level test case are added into svn dinesha 4267d 13h /
26 invalid log files are removed dinesha 4267d 13h /
25 is renamed as tb_top dinesha 4267d 13h /
24 Clean Up dinesha 4267d 13h /
23 Pad sdram clock added and read path register w.r.t pad sdram clock dinesha 4268d 19h /
22 Pad sdram clock added dinesha 4268d 19h /

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