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Rev Log message Author Age Path
44 SDRAM data path logic is modified to support 4 command line pipe line of different bank dinesha 4466d 06h /
43 Test bench automation to handle differ write/read burst sequence is supported now dinesha 4466d 07h /
42 Bug fix in read access is fixed dinesha 4466d 07h /
41 Updated Spec ver 0.1 is added back to svn dinesha 4466d 09h /
40 Application layer Fifo full conditional are register now to synth timing fixes dinesha 4467d 02h /
39 Test Bench upgradation with bigger data burst size dinesha 4467d 02h /
38 Port Name clean up dinesha 4468d 07h /
37 SDRAM dq and sdram pad clock are termindated inside the top rtl files dinesha 4468d 09h /
36 Clean up dinesha 4469d 00h /
35 Updated the New Documents - ver 0.1 dinesha 4469d 01h /
34 Removed the older version dinesha 4469d 01h /
33 clean up dinesha 4469d 02h /
32 Debug is enable through +define dinesha 4471d 01h /
31 Integrated SDRAM controller with wishbone interface is added into SVN dinesha 4471d 01h /
30 test bench file for integrated SDRAM controller with wish bone and Standalone SDRAM controller test bench are added into SVN dinesha 4471d 01h /
29 SDRAM top and core related run file list are added into svn dinesha 4471d 01h /
28 SDRAM top and SDRAM Core Golden files are added into SVN dinesha 4471d 01h /
27 Golden log file corresponds the SDRAM core level test case are added into svn dinesha 4471d 23h /
26 invalid log files are removed dinesha 4471d 23h /
25 tb.sv is renamed as tb_top dinesha 4472d 00h /
24 Clean Up dinesha 4472d 00h /
23 Pad sdram clock added and read path register w.r.t pad sdram clock dinesha 4473d 05h /
22 Pad sdram clock added dinesha 4473d 05h /
21 Clean up dinesha 4473d 05h /
20 8 Bit SDARM support is added dinesha 4475d 00h /
19 8 Bit SDRAM Support added dinesha 4475d 00h /
18 8 Bit SDRAM Support is added dinesha 4475d 00h /
17 micron 8 bit memory models are added into svn dinesha 4475d 00h /
16 8 Bit SDRAM Support is added dinesha 4475d 00h /
15 Port cleanup dinesha 4478d 01h /

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