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Rev Log message Author Age Path
48 top-level cleanup dinesha 4434d 22h /
47 SDRAM bus converter bug fix and top-level signal clean up dinesha 4434d 22h /
46 test bench upgrade + rtl cleanup dinesha 4436d 22h /
45 RTL clean up and logic seperation done from sdram bus converter and request generator dinesha 4437d 03h /
44 SDRAM data path logic is modified to support 4 command line pipe line of different bank dinesha 4439d 01h /
43 Test bench automation to handle differ write/read burst sequence is supported now dinesha 4439d 03h /
42 Bug fix in read access is fixed dinesha 4439d 03h /
41 Updated Spec ver 0.1 is added back to svn dinesha 4439d 04h /
40 Application layer Fifo full conditional are register now to synth timing fixes dinesha 4439d 21h /
39 Test Bench upgradation with bigger data burst size dinesha 4439d 21h /
38 Port Name clean up dinesha 4441d 02h /
37 SDRAM dq and sdram pad clock are termindated inside the top rtl files dinesha 4441d 04h /
36 Clean up dinesha 4441d 19h /
35 Updated the New Documents - ver 0.1 dinesha 4441d 21h /
34 Removed the older version dinesha 4441d 21h /
33 clean up dinesha 4441d 21h /
32 Debug is enable through +define dinesha 4443d 20h /
31 Integrated SDRAM controller with wishbone interface is added into SVN dinesha 4443d 20h /
30 test bench file for integrated SDRAM controller with wish bone and Standalone SDRAM controller test bench are added into SVN dinesha 4443d 20h /
29 SDRAM top and core related run file list are added into svn dinesha 4443d 20h /

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