OpenCores
URL https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk

Subversion Repositories sdr_ctrl

[/] - Rev 50

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
50 Bug fix the request length is fixe dinesha 4552d 00h /
49 clean up dinesha 4552d 23h /
48 top-level cleanup dinesha 4552d 23h /
47 SDRAM bus converter bug fix and top-level signal clean up dinesha 4552d 23h /
46 test bench upgrade + rtl cleanup dinesha 4555d 00h /
45 RTL clean up and logic seperation done from sdram bus converter and request generator dinesha 4555d 04h /
44 SDRAM data path logic is modified to support 4 command line pipe line of different bank dinesha 4557d 02h /
43 Test bench automation to handle differ write/read burst sequence is supported now dinesha 4557d 04h /
42 Bug fix in read access is fixed dinesha 4557d 04h /
41 Updated Spec ver 0.1 is added back to svn dinesha 4557d 05h /
40 Application layer Fifo full conditional are register now to synth timing fixes dinesha 4557d 22h /
39 Test Bench upgradation with bigger data burst size dinesha 4557d 23h /
38 Port Name clean up dinesha 4559d 04h /
37 SDRAM dq and sdram pad clock are termindated inside the top rtl files dinesha 4559d 05h /
36 Clean up dinesha 4559d 20h /
35 Updated the New Documents - ver 0.1 dinesha 4559d 22h /
34 Removed the older version dinesha 4559d 22h /
33 clean up dinesha 4559d 22h /
32 Debug is enable through +define dinesha 4561d 21h /
31 Integrated SDRAM controller with wishbone interface is added into SVN dinesha 4561d 21h /
30 test bench file for integrated SDRAM controller with wish bone and Standalone SDRAM controller test bench are added into SVN dinesha 4561d 21h /
29 SDRAM top and core related run file list are added into svn dinesha 4561d 21h /
28 SDRAM top and SDRAM Core Golden files are added into SVN dinesha 4561d 22h /
27 Golden log file corresponds the SDRAM core level test case are added into svn dinesha 4562d 20h /
26 invalid log files are removed dinesha 4562d 20h /
25 tb.sv is renamed as tb_top dinesha 4562d 20h /
24 Clean Up dinesha 4562d 20h /
23 Pad sdram clock added and read path register w.r.t pad sdram clock dinesha 4564d 01h /
22 Pad sdram clock added dinesha 4564d 01h /
21 Clean up dinesha 4564d 01h /

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.