URL https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk

Subversion Repositories sdr_ctrl

[/] [sdr_ctrl/] - Rev 73

Rev	Log message	Author	Age	Path
73	sdram bug in FPGA mode + 8/16 bit address map fix	dinesha	964d 22h	/sdr_ctrl/
72	Command Clean up for model-sim mode	dinesha	3958d 07h	/sdr_ctrl/
71	Warning cleanup	dinesha	4009d 23h	/sdr_ctrl/
70	Warning Cleanup	dinesha	4009d 23h	/sdr_ctrl/
69	SDRAM address bit increased from 12 bit to 13 bit	dinesha	4010d 00h	/sdr_ctrl/
68	SDRAM Address bit increased from 12 bit to 13 bit	dinesha	4010d 00h	/sdr_ctrl/
67	time scale removed	dinesha	4079d 23h	/sdr_ctrl/
66	dwm tw, bl paramter are passed on the wb2sdrc module	dinesha	4328d 00h	/sdr_ctrl/
65	Updated Log file with CAS latency support 4,5	dinesha	4328d 07h	/sdr_ctrl/
64	CAS Latency support added for 4,5	dinesha	4328d 07h	/sdr_ctrl/
63	FPGA Bench mark results are added	dinesha	4447d 06h	/sdr_ctrl/
62	Synthesis constraint for simplify	dinesha	4447d 07h	/sdr_ctrl/
61	RTL file list are added into SVN	dinesha	4447d 07h	/sdr_ctrl/
60	warning cleanup	dinesha	4447d 07h	/sdr_ctrl/
59	Control path request and data are register now for better FPGA timing	dinesha	4447d 07h	/sdr_ctrl/
58	Read Data is register on RD_FAST=0 case	dinesha	4447d 07h	/sdr_ctrl/
57	Synthesis constraints are added	dinesha	4447d 22h	/sdr_ctrl/
56	FPGA Synth optimisation	dinesha	4447d 23h	/sdr_ctrl/
55	FPGA Synthesis timing optimisation	dinesha	4447d 23h	/sdr_ctrl/
54	FPGA Timing Optimisation	dinesha	4450d 21h	/sdr_ctrl/