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[/] [sdr_ctrl/] - Rev 21

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Rev Log message Author Age Path
21 Clean up dinesha 4563d 09h /sdr_ctrl/
20 8 Bit SDARM support is added dinesha 4565d 04h /sdr_ctrl/
19 8 Bit SDRAM Support added dinesha 4565d 04h /sdr_ctrl/
18 8 Bit SDRAM Support is added dinesha 4565d 04h /sdr_ctrl/
17 micron 8 bit memory models are added into svn dinesha 4565d 04h /sdr_ctrl/
16 8 Bit SDRAM Support is added dinesha 4565d 04h /sdr_ctrl/
15 Port cleanup dinesha 4568d 04h /sdr_ctrl/
14 Unnecessary device config are removed dinesha 4568d 05h /sdr_ctrl/
13 column bit are made progrmmable dinesha 4568d 05h /sdr_ctrl/
12 Column Bits are made programmable dinesha 4568d 05h /sdr_ctrl/
11 SDRAM Specification document added into SVN dinesha 4571d 06h /sdr_ctrl/
10 Waveform files are added into SVN dinesha 4571d 06h /sdr_ctrl/
9 SDR Bus width parameter passing issue across the models are fixed dinesha 4572d 06h /sdr_ctrl/
8 test bench files are added into SVN dinesha 4572d 06h /sdr_ctrl/
7 SDRAM Memory Models are added into SVN dinesha 4572d 06h /sdr_ctrl/
6 Golden Log files are added into SVN dinesha 4572d 06h /sdr_ctrl/
5 Run files are updated into SVN dinesha 4572d 06h /sdr_ctrl/
4 Sdram controller RTL bug fixes done for 16bit SDR Mode dinesha 4573d 03h /sdr_ctrl/
3 SDRAM controller core files are checked in dinesha 4579d 13h /sdr_ctrl/
2 dinesha 4582d 05h /sdr_ctrl/

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